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publication number s25fl004k-016k_00 revision 02 issue date july 14, 2011 s25fl004k / s25fl008k / s25fl016k s25fl004k / s25fl008k / s25fl016k cover sheet 4-mbit / 8-mbit / 16-mbit cmos 3.0 volt flash memory with 104-mhz spi (serial peripher al interface) multi i/o bus data sheet notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informat ion or preliminary designati ons to advise readers of product information or intended s pecifications throughout the produc t life cycle, including development, qualification, initial production, and full production. in all cases, however, reader s are encouraged to verify that they have the latest information before finalizi ng their design. the following descriptions of spansion data sheet designations are presented here to hi ghlight their presenc e and definitions. advance information the advance information designation i ndicates that spansion inc. is de veloping one or more specific products, but has not committed any des ign to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore plac es the following conditions upo n advance information content: ?this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has pr ogressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under c onsideration. spansion places the following conditi ons upon preliminary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designati ons (advance information, preliminary, or full production). th is type of document distinguishes t hese products and their designations wherever necessary, typically on the first page, th e ordering information page, and pages with the dc characteristics table and the ac er ase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of ti me such that no changes or only nominal changes are expected, the preliminary desi gnation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the a ddition or deletion of a speed option, temperat ure range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographic al error or incorrect specificati on. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local sales office.
this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. dee ms the products to have been in sufficient pro- duction volume such that subsequent versions of this document are not expected to change. however, typographical or specificati on corrections, or modifications to the valid com- binations offered may occur. publication number s25fl004k-016k_00 revision 02 issue date july 14, 2011 distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6v read and write operations ? memory architecture ? uniform 4-kb sectors ? 256-byte page size ? program ? page program (up to 256 bytes) in 0.7 ms (typical) ? program operations are on a page by page basis ? quad page programming ? erase ? bulk erase function ? uniform sector erase (4 kb) ? uniform block erase (32 kb and 64 kb) ? erase/program suspend and resume ? cycling endurance ? 100,000 erase/program cycles typical ? data retention ? 20-year data retention typical ? process technology ? manufactured on 0.09 m process technology ? package option ? industry standard pinouts ? 8-pin so package (208 mils) ? 8-pin so package (150 mils) performance characteristics ? speed ? normal read (seria l): 50 mhz clock rate ? fast_read (serial): 104 mhz clock rate (maximum) ? 104 mhz dual spi/quad spi clocks ? 208/416 mhz equivalent dual/quad spi ? 50 mb/s continuous data transfer rate (s25fl004k/s25fl008k) ? 52 mb/s continuous data transfer rate (s25fl016k) ? low power consumption ? 4 ma active current <1 a in deep power-down mode (typical) (s25fl004k/ s25fl016k) 1 a in deep power-down mode (typical) (s25fl008k) ? industrial temperature range (?40c to +85c) ? efficient ?continuous read mode? ? low instruction overhead ? continuous read with 8/16/32/64-byte wrap ? as few as 8 clocks to address memory ? allows true xip (execute in place) operation memory protection features ? advanced security features ? software and hardware write-protect ? top/bottom, 4-kb complement array protection ? power supply lock-down and otp protection ? 64-bit unique id for each device ? discoverable parameters (sfdp) registers ? 3x 256-byte security registers with otp locks ? volatile and non-volatile status register bits s25fl004k / s25fl008k / s25fl016k 4-mbit / 8-mbit / 16-mbit cmos 3.0 volt flash memory with 104-mhz spi (serial peripher al interface) multi i/o bus data sheet
4 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet general description the s25fl004k (4-mbit), s25fl008k (8-mbit), and s25fl01 6k (16-mbit) serial flash memories provide an ideal storage solution for systems with limited spac e, pins and power. the devices offer flexibility and performance well beyond ordinary serial flash devi ces. they are ideal for code shadowing to ram, executing code directly from dual /quad spi (xip) and storing voice, te xt and data. the devices operate on a single 2.7v to 3.6v power supply wi th current consumption as low as 4 ma active and 1 a for deep power- down. all devices are offer ed in space-saving packages. the s25fl004k, s25fl008k, and s25fl016k support the standard serial peripheral interface (spi), and a high performance dual/quad output as well as dual/quad i/o spi: serial cl ock (clk), chip select (cs#), serial data i/o0 (si), i/o1 (so), i/o2 (wp#), and i/ o3 (hold#). spi clock frequencies of up to 104 mhz are supported allowing equivalent clock ra tes of 208 mhz (104 mhz x 2) for dual i/o and 416 mhz (104 mhz x 4) for quad i/o when using the fast read dual/quad i/o instructions. these transfer rates can outperform standard asynchronous 8 and 16-bit parallel flash memori es. the continuous read mode allows for efficient memory access with as few as 8-cloc ks of instruction-overhead to read a 24-bit address, allowing true xip (execute in place) operation. a hold pin, write protect pin and programmable write pr otection, with top or bottom array control, provide further control flexibil ity. additionally, the device supports jedec standard manufacturer and device identification with a 64-bi t unique serial number. s25fl004k the s25fl004k array is organized into 2,048 programma ble pages of 256 bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (4-kb sector er ase), groups of 128 (32-kb block erase), groups of 256 (64-kb block erase) or the entire chip (chip erase). the s25fl004k has 128 erasable sectors and 8 erasable blocks respectively. t he small 4-kb sectors allow for greater flexibility in applications that require data and parameter storage. s25fl008k the s25fl008k array is organized into 4,096 programma ble pages of 256 bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (4-kb sector er ase), groups of 128 (32-kb block erase), groups of 256 (64-kb block erase) or the entire chip (chip erase). the s25fl008k has 256 erasable sectors and 16 erasable blocks respectively. t he small 4-kb sectors allow for greater flexibility in applications that require data and parameter storage. s25fl016k the s25fl016k array is organized into 8,192 programma ble pages of 256 bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (4-kb sector er ase), groups of 128 (32-kb block erase), groups of 256 (64-kb block erase) or the entire chip (chip erase). the s25fl016k has 512 erasable sectors and 32 erasable blocks respectively. t he small 4-kb sectors allow for greater flexibility in applications that require data and parameter storage.
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 5 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 s25fl004k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 s25fl008k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 s25fl016k block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3. input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 spi operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2 write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6. control and status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.1 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.1 write enable (06h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 write enable for volatile status regi ster (50h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 write disable (04h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4 read status register-1 (05h) and read status register-2 (35h) . . . . . . . . . . . . . . . . . . . . . 28 7.5 write status register (01h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.6 read data (03h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.7 fast read (0bh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.8 fast read dual output (3bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.9 fast read quad output (6bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.10 fast read dual i/o (bbh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.11 fast read quad i/o (ebh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.12 word read quad i/o (e7h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.13 octal word read quad i/o (e3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 7.14 set burst with wrap (77h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.15 continuous read mode bits (m7-0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7.16 continuous read mode reset (ffh or ffffh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.17 page program (02h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 7.18 quad page program (32h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.19 sector erase (20h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 7.20 32 kb block erase (52h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7.21 64 kb block erase (d8h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 7.22 chip erase (c7h / 60h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 7.23 erase / program suspend (75h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 7.24 erase / program resume (7ah). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7.25 deep power-down (b9h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.26 release from deep power-down / device id (abh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.27 read manufacturer / device id (90h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.28 read manufacturer / device id dual i/o (92h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.29 read manufacturer / device id quad i/o (94h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.30 read unique id number (4bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.31 read jedec id (9fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.32 read sfdp register (5ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.33 erase security registers (44h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 7.34 program security registers (42h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 7.35 read security registers (48h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.2 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 8.3 power-up timing and writ e inhibit threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.4 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.5 ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 8.6 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8.7 serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.8 serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.9 hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 9. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 9.1 soa008 narrow ? 8-pin plastic small outline packag e (150-mils body width) . . . . . . . . . 67 9.2 soc008 wide ? 8-pin plasti c small outline package (208-mils body width) . . . . . . . . . . . 68 10. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 7 data sheet figures figure 2.1 8-pin plastic small outline package (so) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 6.1 status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 6.2 status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7.1 write enable instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 figure 7.2 write enable for volatile st atus register instruction sequence di agram . . . . . . . . . . . . . . . 27 figure 7.3 write disable instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 figure 7.4 read status register instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 7.5 write status r egister instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 7.6 read data instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 figure 7.7 fast read instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 7.8 fast read dual output instruction sequence diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 7.9 fast read quad output instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 7.10 fast read dual i/o in struction sequence (i nitial instruction or previous m5-4 ? 10) . . . . . . 33 figure 7.11 fast read dual i/ o instruction sequence (previous instruction set m5-4 = 10) . . . . . . . . . . 34 figure 7.12 fast read quad i/o in struction sequence (initial in struction or previous m5-4 ? 10) . . . . . . 35 figure 7.13 fast read quad i/o instruct ion sequence (previous instruction set m5-4 = 10) . . . . . . . . . 35 figure 7.14 word read quad i/o instruction se quence (initial instructi on or previous m5-4 ? 10) . . . . . 36 figure 7.15 word read quad i/o instruction sequence (pre vious instruction set m5-4 = 10). . . . . . . . . 37 figure 7.16 octal word read quad i/o instruction s equence (initial instruct ion or previous m5-4 ? 10) 38 figure 7.17 octal word read quad i/o in struction sequence (previous instruction set m5-4 = 10) . . . . 38 figure 7.18 set burst with wrap instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 7.19 continuous read mode reset for fast read dual/q uad i/o . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 7.20 page program instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 7.21 quad page program inst ruction sequence diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 7.22 sector erase instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 7.23 32 kb block erase instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 7.24 64 kb block erase instruction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 7.25 chip erase instructi on sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 7.26 erase/program suspend instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 7.27 erase/program resume instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 7.28 deep power-down instruction sequ ence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 7.29 release from deep power-down instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 7.30 release from deep power-down / device id in struction sequence diagram . . . . . . . . . . . . 50 figure 7.31 read manufacturer / device id diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 7.32 read manufacturer / device id dual i/o diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 7.33 read manufacturer / device id quad i/o diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 7.34 read unique id number instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 7.35 read jedec id instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 7.36 read sfdp register in struction sequence diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 7.37 erase security registers instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 7.38 program security registers inst ruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 7.39 read security register s instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 figure 8.1 power-up timing and voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 8.2 ac measurement i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 8.3 serial output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 8.4 serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 8.5 hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
8 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet tables table 3.1 8-pin soic 150-mil / 208-mil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 4.1 s25fl004k, s25fl008k, and s25fl016k valid combinations . . . . . . . . . . . . . . . . . . . . . .13 table 6.1 status register protection bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 table 6.2 s25fl004k status register memory protection (cmp = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 6.3 s25fl008k status register memory protection (cmp = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .20 table 6.4 s25fl016k status register memory protection (cmp = 0) . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 6.5 s25fl004k status register memory protection (cmp = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 6.6 s25fl008k status register memory protection (cmp = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .22 table 6.7 s25fl016k status register memory protection (cmp = 1) . . . . . . . . . . . . . . . . . . . . . . . . . .23 table 7.1 manufacturer identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7.2 device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7.3 instruction set (era se, program instructions (1) ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 table 7.4 instruction set (read instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 7.5 instruction set (id, security instructions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 table 7.6 serial flash discoverable paramete r definition table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 8.1 ac electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 9 data sheet 1. block diagrams 1.1 s25fl004k block diagram 00 3 000h 00 3 0ffh 002000h 0020ffh 001000h 0010ffh col u mn decode and 256- b yte p a ge b u ffer beginning p a ge addre ss ending p a ge addre ss s 25fl0040k s pi comm a nd & control logic byte addre ss l a tch / co u nter s t a t us regi s ter write control logic p a ge addre ss l a tch / co u nter s o (io1) s i (io0) c s # clk hold# (io 3 ) wp (io2) high volt a ge gener a tor s xx0f00h xx0fffh ? s ector 0 (4 kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? s ector 1 (4 kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? s ector 2 (4 kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? s ector 1 3 (4 kb) ? xxd000h xxd0ffh xxef00h xxefffh ? s ector 14 (4 kb) ? xxe000h xxe0ffh xxff00h xxffffh ? s ector 15 (4 kb) ? xxf000h xxf0ffh block s egment a tion d a t a s ec u rity regi s ter 1 - 3 write protect logic a nd row decode 000000h 0000ffh s fdp regi s ter 00ff00h 00ffffh ? block 0 (64 kb) ? 000000h 0000ffh 01ff00h 01ffffh ? block 1 (64 kb) ? 010000h 0100ffh ? ? ? 0 3 ff00h 0 3 ffffh ? block 3 (64 kb) ? 0 3 0000h 0 3 00ffh 04ff00h 04ffffh ? block 4 (64 kb) ? 040000h 0400ffh ? ? ? 07ff00h 07ffffh ? block 7 (64 kb) ? 070000h 0700ffh 00 3 000h 00 3 0ffh 002000h 0020ffh 001000h 0010ffh xx0f00h xx0fffh xx0000h xx00ffh xx1f00h xx1fffh xx1000h xx10ffh xx2f00h xx2fffh xx2000h xx20ffh ? ? ? xxdf00h xxdfffh xxd000h xxd0ffh xxef00h xxefffh xxe000h xxe0ffh xxff00h xxffffh xxf000h xxf0ffh block s egment a tion d a t a s ec u rity regi s ter 1 - 3 write protect logic a nd row decode 000000h 0000ffh s fdp regi s ter 00ff00h 00ffffh 000000h 0000ffh 01ff00h 01ffffh 010000h 0100ffh ? ? ? 0 3 ff00h 0 3 ffffh 0 3 0000h 0 3 00ffh 04ff00h 04ffffh 040000h 0400ffh ? ? ? 07ff00h 07ffffh 070000h 0700ffh
10 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 1.2 s25fl008k block diagram 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh column decode and 256-byte page buffer beginning page address ending page address s25fl008k spi command & control logic byte address latch / counter status register write control logic page address latch / counter so (io1) si (io0) cs# clk hold# (io3) wp# (io2) high voltage generators xx0f00h xx0fffh ? sector 0 (4 kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? sector 1 (4 kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? sector 2 (4 kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? sector 13 (4 kb) ? xxd000h xxd0ffh xxef00h xxefffh ? sector 14 (4 kb) ? xxe000h xxe0ffh xxff00h xxffffh ? sector 15 (4 kb) ? xxf000h xxf0ffh block segmentation data security register 1 - 3 write protect logic and row decode 000000h 0000ffh sfdp register 00ff00h 00ffffh ? block 0 (64 kb) ? 000000h 0000ffh ? ? ? 03ff00h 03ffffh ? block 3 (64 kb) ? 030000h 0300ffh 04ff00h 04ffffh ? block 4 (64 kb) ? 040000h 0400ffh ? ? ? 07ff00h 07ffffh ? block 7 (64 kb) ? 070000h 0700ffh 08ff00h 08ffffh ? block 8 (64 kb) ? 080000h 0800ffh ? ? ? 0fff00h 0fffffh ? block 15 (64 kb) ? 0f0000h 0f00ffh 003000h 0030ffh 002000h 0020ffh 001000h 0010ffh beginning page address ending page address clk xx0f00h xx0fffh xx0000h xx00ffh xx1f00h xx1fffh xx1000h xx10ffh xx2f00h xx2fffh xx2000h xx20ffh ? ? ? xxdf00h xxdfffh xxd000h xxd0ffh xxef00h xxefffh xxe000h xxe0ffh xxff00h xxffffh xxf000h xxf0ffh block segmentation data security register 1 - 3 write protect logic and row decode 000000h 0000ffh sfdp register 00ff00h 00ffffh 000000h 0000ffh ? ? ? 03ff00h 03ffffh 030000h 0300ffh 04ff00h 04ffffh 040000h 0400ffh ? ? ? 07ff00h 07ffffh 070000h 0700ffh 08ff00h 08ffffh 080000h 0800ffh ? ? ? 0fff00h 0fffffh 0f0000h 0f00ffh
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 11 data sheet 1.3 s25fl016k block diagram 00 3 000h 00 3 0ffh 002000h 0020ffh 001000h 0010ffh col u mn decode and 256- b yte p a ge b u ffer beginning p a ge addre ss ending p a ge addre ss s 25fl016k s pi comm a nd & control logic byte addre ss l a tch / co u nter s t a t us regi s ter write control logic p a ge addre ss l a tch / co u nter s o (io1) c s # clk hold# (io 3 ) wp# (io2) high volt a ge gener a tor s xx0f00h xx0fffh ? s ector 0 (4 kb) ? xx0000h xx00ffh xx1f00h xx1fffh ? s ector 1 (4 kb) ? xx1000h xx10ffh xx2f00h xx2fffh ? s ector 2 (4 kb) ? xx2000h xx20ffh ? ? ? xxdf00h xxdfffh ? s ector 1 3 (4 kb) ? xxd000h xxd0ffh xxef00h xxefffh ? s ector 14 (4 kb) ? xxe000h xxe0ffh xxff00h xxffffh ? s ector 15 (4 kb) ? xxf000h xxf0ffh block s egment a tion d a t a s ec u rity regi s ter 1 - 3 write protect logic a nd row decode 00ff00h 00ffffh ? block 0 (64 kb) ? 000000h 0000ffh ? ? ? 07ff00h 07ffffh ? block 7 (64 kb) ? 070000h 0700ffh 0 8 ff00h 0 8 ffffh ? block 8 (64 kb) ? 0 8 0000h 0 8 00ffh ? ? ? 0fff00h 0fffffh ? block 15 (64 kb) ? 0f0000h 0f00ffh 10ff00h 10ffffh ? block 16 (64 kb) ? 100000h 1000ffh ? ? ? 1fff00h 1fffffh ? block 3 1 (64 kb) ? 1f0000h 1f00ffh 000000h 0000ffh s fdp regi s ter 00 3 000h 00 3 0ffh 002000h 0020ffh 001000h 0010ffh beginning p a ge addre ss ending p a ge addre ss byte addre ss l a tch / co u nter s i (io0) clk xx0f00h xx0fffh xx0000h xx00ffh xx1f00h xx1fffh xx1000h xx10ffh xx2f00h xx2fffh xx2000h xx20ffh ? ? ? xxdf00h xxdfffh xxd000h xxd0ffh xxef00h xxefffh xxe000h xxe0ffh xxff00h xxffffh xxf000h xxf0ffh block s egment a tion d a t a s ec u rity regi s ter 1 - 3 write protect logic a nd row decode 00ff00h 00ffffh 000000h 0000ffh ? ? ? 07ff00h 07ffffh 070000h 0700ffh 0 8 ff00h 0 8 ffffh 0 8 0000h 0 8 00ffh ? ? ? 0fff00h 0fffffh 0f0000h 0f00ffh 10ff00h 10ffffh 100000h 1000ffh ? ? ? 1fff00h 1fffffh 1f0000h 1f00ffh 000000h 0000ffh s fdp regi s ter
12 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 2. connection diagrams figure 2.1 8-pin plastic small outline package (so) 3. input/output descriptions notes: 1. io0 and io1 are used for standard and dual spi instructions. 2. io0 ? io3 are used for quad spi instructions. 1 2 3 4 c s # s o (io1) wp# (io2) gnd s i (io0) clk hold# (io 3 ) vcc 5 6 7 8 table 3.1 8-pin soic 150-mil / 208-mil pin no. pin name i/o function 1 cs# i chip select input 2 so (io1) i/o data output (data input output 1) (1) 3 wp# (io2) i/o write protect input (data input output 2) (2) 4 gnd ground 5 si (io0) i/o data input (data input output 0) (1) 6 clk i serial clock input 7 hold# (io3) i/o hold input (data input output 3) (2) 8 vcc power supply
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 13 data sheet 4. ordering information the ordering part number is formed by a valid combination of the following: 4.1 valid combinations table 4.1 lists the valid combinations co nfigurations planned to be support ed in volume for this device. s25fl 016 k 0x m f i 01 1 packing type 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 01 = 8-pin so package (208 mil) 04 = 8-pin so package (150 mil) temperature range i = industrial (?40c to +85c) package materials f = lead (pb)-free package type m = 8-pin so package speed 0x = 104 mhz device technology k = 0.09 m process technology density 004 = 4 mbit 008 = 8 mbit 016 = 16 mbit device family s25fl spansion memory 3.0 volt-only, serial peripheral interface (spi) flash memory table 4.1 s25fl004k, s25fl008k, and s25fl016k valid combinations valid combinations package marking base ordering part number speed option package & temperature model number packing type s25fl004k 0x mfi 01, 04 0, 1, 3 fl004kif s25fl008k 0x mfi 01, 04 0, 1, 3 fl008kif s25fl016k 0x mfi 01, 04 0, 1, 3 fl016kif
14 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 5. functional description 5.1 spi operations 5.1.1 standard spi instructions the s25fl004k/s25fl008k/s25fl016k is accessed thro ugh an spi compatible bus consisting of four signals: serial clock (clk), chip select (cs#), serial data input (si) and serial data output (so). standard spi instructions use the si input pin to serially write instru ctions, addresses or data to the device on the rising edge of clk. the so output pin is used to read data or status from the device on the falling edge clk. spi bus operation mode 0 (0,0) and 3 (1,1) are support ed. the primary differenc e between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0, the clk si gnal is normally low on the falling and rising edges of cs#. for mode 3, the clk signal is normall y high on the falling and rising edges of cs#. 5.1.2 dual spi instructions the s25fl004k/s25fl008k/s25fl016k supports dual spi operation when using the ?fast read dual output (3bh)? and ?fast read dual i/o (bbh)? instructio ns. these instructions allow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devices. the dual spi read instructions are ideal fo r quickly downloading code to ram upon power-up (code-shadowing) or for executing non-speed-critical code di rectly from the spi bus (xip). when using dual spi instructions, the si and so pins become bidirectional i/o pins: io0 and io1. 5.1.3 quad spi instructions the s25fl004k/s25fl008k/s25fl016k supports quad spi operation when using the ?fast read quad output (6bh)?, ?fast read quad i/o (ebh)?, ?word read quad i/o (e7h)? and ?octal word read quad i/o (e3h)? instructions. these instructions allow data to be tr ansferred to or from the dev ice four to six times the rate of ordinary serial flash. th e quad read instructions offer a signif icant improvement in continuous and random access transfer rates allowing fast code-shadow ing to ram or execution directly from the spi bus (xip). when using quad spi instructions the si and so pins become bidirectional io0 and io1, and the wp# and hold# pins become io2 and io3 respectively. q uad spi instructions requi re the non-volatile quad enable bit (qe) in status register-2 to be set. 5.1.4 hold function for standard spi and dual spi operations, the hold# signal allows the s25fl004k/s25fl008k/ s25fl016k operation to be paused while it is actively selected (when cs# is low). the hold# function may be useful in cases where the spi data and clock signals are shared with other device s. for example, consider if the page buffer was only partially wri tten when a priority interrupt requires use of the spi bus. in this case the hold# function can save the state of the instru ction and the data in the bu ffer so programming can resume where it left off once the bus is available ag ain. the hold# function is on ly available for standard spi and dual spi operation, not during quad spi. to initiate a hold# condition, the device must be select ed with cs# low. a hold# condition will activate on the falling edge of the hold# signal if the clk signal is already low. if the clk is not already low the hold# condition will activate after the next falling edge of clk. the hold# condition will terminate on the rising edge of the hold# signal if the clk si gnal is already low. if the clk is not already low the hold# condition will terminate after the next falling edge of clk. during a hold# condition, the serial data output (so) is high impedance, and serial data input (s i) and serial clock (clk) are igno red. the chip select (cs#) signal should be kept active (low) for the full duration of the hold# operation to avoid resetting the internal logic state of the device.
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 15 data sheet 5.2 write protection applications that use non-vo latile memory must take into consider ation the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern, the s25fl004k/ s25fl008k/s25fl016k provides several means to protect the data from inadvertent writes. 5.2.1 write protect features ? device resets when v cc is below threshold ? time delay write disable after power-up ? write enable/disable instructions and automat ic write disable after erase or program ? software and hardware (wp# pin) writ e protection using status register ? write protection using deep power-down instruction ? lock down write protection until next power-up ? one time program (otp) write protection upon power-up or at power-down, the s25fl004k/s2 5fl008k/s25fl016k will maintain a reset condition while v cc is below the threshold value of vwi, (see figure 8.1, power-up timing and voltage levels on page 62 ). while reset, all operations are disabled an d no instructions are re cognized. during power-up and after the v cc voltage exceeds vwi, all program and erase re lated instructions are further disabled for a time delay of t puw . this includes the write enable, page progr am, sector erase, block erase, chip erase and the write status regist er instructions. note that the chip select pin (cs#) must track the v cc supply level at power-up until the v cc -min level and t vsl time delay is reached. if needed a pull-up resistor on cs# can be used to accomplish this. after power-up the device is automatica lly placed in a write- disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be is sued before a page program, sector erase, block erase, chip erase or write status register instructi on will be accepted. after completing a program, erase or write inst ruction the write enable latch (wel) is automatically cleared to a write-disabled state of 0. software controlled write protection is facilitated using the write status register instructio n and setting the status register protect (srp0, srp1) and block protect (cmp, sec,tb, bp2, bp1 and bp0) bits. these settings allow a portion as small as 4-kb sector or the entire memory array to be configured as read only. used in conjunction with the write protect (wp#) pi n, changes to the status register can be enabled or disabled under hardware control. see status register on page 16. for further information. additionally, the deep power-down instruction offers an extra level of wr ite protection as all instru ctions are ignored except for the release from deep power-down instruction. 6. control and status registers the read status register-1 and status register-2 instructions can be used to provide status on the availability of the flash memory array, if the device is write enabled or disabled, the state of write protection, quad spi setting, security regist er lock status and eras e/program suspend stat us. the write status register instruction can be used to configure the device write protec tion features, quad spi setting and security register otp lock. write access to the status register is controlled by t he state of the non-volatile status register protect bits (srp 0, srp1), the write enable instruct ion, and during standard/dual spi operations, the wp# pin.
16 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 6.1 status register 6.1.1 busy busy is a read only bit in the status register (s0) that is set to a 1 stat e when the device is executing a page program, quad page program, sector er ase, block erase, chip erase, write status register or erase/ program security register instruction. during this time the device will ignor e further instructi ons except for the read status register and erase/ program suspend instruction (see t w , t pp , t se , t be , and t ce in section 8.6, ac electrical characteristics on page 64 ). when the program, er ase or write status /security register instruction has completed, the busy bi t will be cleared to a 0 state indicati ng the device is ready for further instructions. 6.1.2 write enable latch (wel) write enable latch (wel) is a read only bi t in the status register (s1) that is set to 1 after executing a write enable instruction. the wel status bit is cleared to 0 when the device is write disa bled. a write disable state occurs upon power-up or after any of the following in structions: write disable, page program, quad page program, sector erase, block erase, chip erase, write status register, erase secu rity register and program security register. 6.1.3 block protect bits (bp2, bp1, bp0) the block protect bits (bp2, bp1, bp0) are non-volatile re ad/write bits in the status register (s4, s3, and s2) that provide write prot ection control and status. block protect bits can be set usi ng the write status register instruction (see t w in ac electrical characteristics on page 64 ). all, none or a portion of the memory array can be protected from program and erase instructions (see table 6.3 on page 20 ). the factory default setting for the block protection bits is 0 (none of the array is protected.) 6.1.4 top/bottom block protect (tb) the non-volatile top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in table 6.1, status register prot ection bits on page 17 . the factory default setting is tb=0. the tb bit can be set with the write status register instruction depending on the state of the srp0, srp1 and wel bits. 6.1.5 sector/block protect (sec) the non-volatile sector/block protect bit (sec) contro ls if the block protect bits (bp2, bp1, bp0) protect either 4-kb sectors ( sec=1) or 64-kb blocks (sec=0) in the top (tb=0) or the bott om (tb=1) of the array as shown in table 6.1 . the default setting is sec=0. 6.1.6 complement protect (cmp) the complement protect bit (cmp) is a non-volatile read/wr ite bit in the status regi ster (s14). it is used in conjunction with sec, tb, bp2, bp1 and bp0 bits to pr ovide more flexibility for t he array protection. once cmp is set to 1, previous array pr otection set by sec, tb, bp2, bp1 and bp0 will be reversed. for instance, when cmp=0, a top 4-kb sector can be protected while the rest of the arra y is not; when cmp=1, the top 4-kb sector will become unprotected while the rest of the array become read- only. please refer to table 6.1 for details. the default setting is cmp=0.
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 17 data sheet 6.1.7 status register protect (srp1, srp0) the status register protect bits (s rp1 and srp0) are non-volatile read/write bits in the status register (s8 and s7). the srp bits control the meth od of write protection: so ftware protection, hard ware protection, power supply lock-down or one time programmable (otp) protection. notes: 1. when srp1, srp0 = (1, 0), a power-down, power- up cycle will change srp1, srp0 to (0, 0) state. 2. this feature is available upon special order. please contact spansion for details. 6.1.8 erase/program suspend status (sus) the suspend status bit is a read only bit in the status register (s15) that is set to 1 after executing a erase/ program suspend (75h) instruction. the sus status bit is clea red to 0 by erase/program resume (7ah) instruction as well as a power-down, power-up cycle. 6.1.9 security register lock bits (lb3, lb2, lb1) the security register lock bits (lb3 , lb2, lb1) are non-volatile one ti me program (otp) bits in status register (s13, s12, s11) that provide the write protect control and status to the security registers. the default state of lb[3:1] is 0, security registers are unlocked. lb[3:1] can be set to 1 individually using the write status register instruction. lb[3:1] are one time programmable (otp), once it?s set to 1, the corresponding 256-byte security regist er will become read-only permanently. 6.1.10 quad enable (qe) the quad enable (qe) bit is a non-volatile read/write bit in the status register (s9) that allows quad spi operation. when the qe bit is set to a 0 state (facto ry default), the wp# pin an d hold# are enabled. when the qe bit is set to a 1, the quad io2 and io3 pins are enabled, and wp# and ho ld# functions are disabled. note : if the wp# or hold# pins are tied directly to t he power supply or ground du ring standard spi or dual spi operation, the qe bit should never be set to a 1. table 6.1 status register protection bits srp1 srp0 wp# status register description 0 0 x software protection wp# pin has no control. the status register can be written to after a write enable instruction, wel=1. [factory default] 0 1 0 hardware protected when wp# pin is low the status register locked and can not be written to. 0 1 1 hardware unprotected when wp# pin is high the status register is unlocked and can be written to after a write enable instruction, wel=1. 10x power supply lock- down status register is protected and can not be written to again until the next power-down, power-up cycle. (1) 1 1 x one time program (2) status register is permanently protected and can not be written to.
18 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet figure 6.1 status register 1 figure 6.2 status register 2 s 7 s 6 s 5 s 4 s3 s 2 s 1 s 0 s rp0 s ec tb bp2 bp1 bp0 wel bu s y s t a t us regi s ter protect 0 (non-vol a tile) s ector protect (non-vol a tile) top/bottom protect (non-vol a tile) block protect bit s (non-vol a tile) write en ab le l a tch er as e/write in progre ss s 7 s 6 s 5 s 4 s3 s 2 s 1 s 0 s rp0 s ec tb bp2 bp1 bp0 wel bu s y s 15 s 14 s 1 3 s 12 s 11 s 10 s 9 s8 s u s cmp lb 3 lb2 lb1 (r) qe s rp1 sus pend s t a t us complement p rotect (non-vol a tile) s ec u rity regi s ter lock bit s (non-vol a tile otp) q ua d en ab le (non-vol a tile) s t a t us regi s ter protect 1 ( non-vol a tile ) re s erved s 15 s 14 s 1 3 s 12 s 11 s 10 s 9 s8 s u s cmp lb 3 lb2 lb1 (r) qe s rp1 (
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 19 data sheet notes: 1. x = don?t care. 2. if any erase or program command specifies a memory region t hat contains protect ed data portion, this command will be ignored. table 6.2 s25fl004k status register me mory protection (cmp = 0) status register (1) s25fl004k (4 mbit) memory protection (2) sec tb bp2 bp1 bp0 block(s) addresses density portion x x 0 0 0 none none none none 0 0 0 0 1 7 070000h ? 07ffffh 64 kb upper 1/8 0 0 0 1 0 6 and 7 060000h ? 07ffffh 128 kb upper 1/4 0 0 0 1 1 4 thru 7 040000h ? 07ffffh 256 kb upper 1/2 0 1 0 0 1 0 000000h ? 00ffffh 64 kb lower 1/8 0 1 0 1 0 0 and 1 000000h ? 01ffffh 128 kb lower 1/4 0 1 0 1 1 0 thru 3 000000h ? 03ffffh 256 kb lower 1/2 0 x 1 x x 0 thru 7 000000h ? 07ffffh 512 kb all 1 0 0 0 1 7 07f000h ? 07ffffh 4 kb upper 1/128 1 0 0 1 0 7 07e000h ? 07ffffh 8 kb upper 1/64 1 0 0 1 1 7 07c000h ? 07ffffh 16 kb upper 1/32 1 0 1 0 x 7 078000h ? 07ffffh 32 kb upper 1/16 1 0 1 1 0 7 078000h ? 07ffffh 32 kb upper 1/16 1 1 0 0 1 0 000000h ? 000fffh 4 kb lower 1/128 1 1 0 1 0 0 000000h ? 001fffh 8 kb lower 1/64 1 1 0 1 1 0 000000h ? 003fffh 16 kb lower 1/32 1 1 1 0 x 0 000000h ? 007fffh 32 kb lower 1/16 1 1 1 1 0 0 000000h ? 007fffh 32 kb lower 1/16 1 x 1 1 1 0 thru 7 000000h ? 07ffffh 512 kb all
20 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet notes: 1. x = don?t care. 2. if any erase or program command specifies a memory region t hat contains protect ed data portion, this command will be ignored. table 6.3 s25fl008k status register me mory protection (cmp = 0) status register (1) s25fl008k (8 mbit) memory protection (2) sec tb bp2 bp1 bp0 block(s) addresses density portion x x 0 0 0 none none none none 0 0 0 0 1 15 0f0000h ? 0fffffh 64 kb upper 1/16 0 0 0 1 0 14 and 15 0e0000h ? 0fffffh 128 kb upper 1/8 0 0 0 1 1 12 thru 15 0c0000h ? 0fffffh 256 kb upper 1/4 0 0 1 0 0 8 thru 15 080000h ? 0fffffh 512 kb upper 1/2 0 1 0 0 1 0 000000h ? 00ffffh 64 kb lower 1/16 0 1 0 1 0 0 and 1 000000h ? 01ffffh 128 kb lower 1/8 0 1 0 1 1 0 thru 3 000000h ? 03ffffh 256 kb lower 1/4 0 1 1 0 0 0 thru 7 000000h ? 07ffffh 512 kb lower 1/2 0 x 1 0 1 0 thru 15 000000h ? 0fffffh 1 mb all x x 1 1 x 0 thru 15 000000h ? 0fffffh 1 mb all 1 0 0 0 1 15 0ff000h ? 0fffffh 4 kb upper 1/256 1 0 0 1 0 15 0fe000h ? 0fffffh 8 kb upper 1/128 1 0 0 1 1 15 0fc000h ? 0fffffh 16 kb upper 1/64 1 0 1 0 x 15 0f8000h ? 0fffffh 32 kb upper 1/32 1 1 0 0 1 0 000000h ? 000fffh 4 kb lower 1/256 1 1 0 1 0 0 000000h ? 001fffh 8 kb lower 1/128 1 1 0 1 1 0 000000h ? 003fffh 16 kb lower 1/64 1 1 1 0 x 0 000000h ? 007fffh 32 kb lower 1/32
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 21 data sheet notes: 1. x = don?t care. 2. if any erase or program command specifies a memory region t hat contains protect ed data portion, this command will be ignored. table 6.4 s25fl016k status register me mory protection (cmp = 0) status register (1) s25fl016k (16 mbit) memory protection (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 none none none none 0 0 0 0 1 31 1f0000h ? 1fffffh 64 kb upper 1/32 0 0 0 1 0 30 and 31 1e0000h ? 1fffffh 128 kb upper 1/16 0 0 0 1 1 28 thru 31 1c0000h ? 1fffffh 256 kb upper 1/8 0 0 1 0 0 24 thru 31 180000h ? 1fffffh 512 kb upper 1/4 0 0 1 0 1 16 thru 31 100000h ? 1fffffh 1 mb upper 1/2 0 1 0 0 1 0 000000h ? 00ffffh 64 kb lower 1/32 0 1 0 1 0 0 and 1 000000h ? 01ffffh 128 kb lower 1/16 0 1 0 1 1 0 thru 3 000000h ? 03ffffh 256 kb lower 1/8 0 1 1 0 0 0 thru 7 000000h ? 07ffffh 512 kb lower 1/4 0 1 1 0 1 0 thru 15 000000h ? 0fffffh 1 mb lower 1/2 x x 1 1 x 0 thru 31 000000h ? 1fffffh 2 mb all 1 0 0 0 1 31 1ff000h ? 1fffffh 4 kb upper 1/512 1 0 0 1 0 31 1fe000h ? 1fffffh 8 kb upper 1/256 1 0 0 1 1 31 1fc000h ? 1fffffh 16 kb upper 1/128 1 0 1 0 x 31 1f8000h ? 1fffffh 32 kb upper 1/64 1 1 0 0 1 0 000000h ? 000fffh 4 kb lower 1/512 1 1 0 1 0 0 000000h ? 001fffh 8 kb lower 1/256 1 1 0 1 1 0 000000h ? 003fffh 16 kb lower 1/128 1 1 1 0 x 0 000000h ? 007fffh 32 kb lower 1/64
22 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet notes: 1. x = don?t care. 2. if any erase or program command specifies a memory region t hat contains protect ed data portion, this command will be ignored. notes: 1. x = don?t care. 2. if any erase or program command specifies a memory region t hat contains protect ed data portion, this command will be ignored. table 6.5 s25fl004k status register me mory protection (cmp = 1) status register (1) s25fl004k (4 mbit) memory protection (2) sec tb bp2 bp1 bp0 block(s) addresses density portion x x 0 0 0 0 thru 7 000000h ? 07ffffh 512 kb all 0 0 0 0 1 0 thru 6 000000h ? 06ffffh 448 kb lower 7/8 0 0 0 1 0 0 thru 5 000000h ? 05ffffh 384 kb lower 3/4 0 0 0 1 1 0 thru 3 000000h ? 03ffffh 256 kb lower 1/2 0 1 0 0 1 1 thru 7 010000h ? 07ffffh 448 kb upper 7/8 0 1 0 1 0 2 thru 7 020000h ? 07ffffh 384 kb upper 3/4 0 1 0 1 1 4 thru 7 040000h ? 07ffffh 256 kb upper 1/2 1 0 0 0 1 0 thru 7 000000h ? 07efffh 508 kb lower 127/128 1 0 0 1 0 0 thru 7 000000h ? 07dfffh 504 kb lower 63/64 1 0 0 1 1 0 thru 7 000000h ? 07bfffh 496 kb lower 31/32 1 0 1 0 x 0 thru 7 000000h ? 077fffh 480 kb lower 15/16 1 0 1 1 0 0 thru 7 000000h ? 077fffh 480 kb lower 15/16 1 1 0 0 1 0 thru 7 001000h ? 07ffffh 508 kb upper 127/128 1 1 0 1 0 0 thru 7 002000h ? 07ffffh 504 kb upper 63/64 1 1 0 1 1 0 thru 7 004000h ? 07ffffh 496 kb upper 31/32 1 1 1 0 x 0 thru 7 008000h ? 07ffffh 480 kb upper 15/16 1 1 1 1 0 0 thru 7 008000h ? 07ffffh 480 kb upper 15/16 x x 1 1 1 none none none none table 6.6 s25fl008k status register me mory protection (cmp = 1) status register (1) s25fl008k (8 mbit) memory protection (2) sec tb bp2 bp1 bp0 block(s) addresses density portion x x 0 0 0 0 thru 15 000000h ? 0fffffh 1 mb all 0 0 0 0 1 0 thru 14 000000h ? 0effffh 960 kb lower 15/16 0 0 0 1 0 0 thru 13 000000h ? 0dffffh 896 kb lower 7/8 0 0 0 1 1 0 thru 11 000000h ? 0bffffh 768 kb lower 3/4 0 0 1 0 0 0 thru 7 000000h ? 07ffffh 512 kb lower 1/2 0 1 0 0 1 1 thru 15 010000h ? 0fffffh 960 kb upper 15/16 0 1 0 1 0 2 thru 15 020000h ? 0fffffh 896 kb upper 7/8 0 1 0 1 1 4 thru 15 040000h ? 0fffffh 768 kb upper 3/4 0 1 1 0 0 8 thru 15 080000h ? 0fffffh 512 kb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 thru 15 000000h ? 0fefffh 1,020 kb lower 255/256 1 0 0 1 0 0 thru 15 000000h ? 0fdfffh 1,016 kb lower 127/128 1 0 0 1 1 0 thru 15 000000h ? 0fbfffh 1,008 kb lower 63/64 1 0 1 0 x 0 thru 15 000000h ? 0f7fffh 992 kb lower 31/32 1 1 0 0 1 0 thru 15 001000h ? 0fffffh 1,020 kb upper 255/256 1 1 0 1 0 0 thru 15 002000h ? 0fffffh 1,016 kb upper 127/128 1 1 0 1 1 0 thru 15 004000h ? 0fffffh 1,008 kb upper 63/64 1 1 1 0 x 0 thru 15 008000h ? 0fffffh 992 kb upper 31/32
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 23 data sheet notes: 1. x = don?t care. 2. if any erase or program command specifies a memory region t hat contains protect ed data portion, this command will be ignored. 7. instructions the instruction set of the s25fl004k, s25fl008k, and s25f l008k consist of thirty five basic instructions that are fully controll ed through the spi bus (see table 7.3 to table 7.5 on page 26 ). instructions are initiated with the falling edge of chip select (cs#). the first by te of data clocked into the si input provides the instruction code. data on the si input is sampled on the rising edge of clo ck with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by address bytes, data bytes, dummy bytes (don?t care), and in some cases, a combination. instructions are completed with the rising edge of edge cs#. clock relati ve timing diagrams for each instruct ion are included in the figures below. all read instructions can be completed af ter any clocked bit. however, all in structions that wr ite, program or erase must complete on a byte boundary (cs# driven hi gh after a full 8 bits have been clocked) otherwise the instruction will be ignored. this feature further protects the device from inadvertent writes. additi onally, while the memory is being programmed or er ased, or when the status register is being written, all instructions except for read status register will be ignored until the program or er ase cycle has completed. table 6.7 s25fl016k status register me mory protection (cmp = 1) status register (1) s25fl016k (16 mbit) memory protection (2) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 0 thru 31 000000h ? 1fffffh all all 0 0 0 0 1 0 thru 30 000000h ? 1effffh 1,984 kb lower 31/32 0 0 0 1 0 0 thru 29 000000h ? 1dffffh 1,920 kb lower 15/16 0 0 0 1 1 0 thru 27 000000h ? 1bffffh 1,792 kb lower 7/8 0 0 1 0 0 0 thru 23 000000h ? 17ffffh 1,536 kb lower 3/4 0 0 1 0 1 0 thru 15 000000h ? 0fffffh 1 mb lower 1/2 0 1 0 0 1 1 thru 31 010000h ? 1fffffh 1,984 kb upper 31/32 0 1 0 1 0 2 and 31 020000h ? 1fffffh 1,920 kb upper 15/16 0 1 0 1 1 4 thru 31 040000h ? 1fffffh 1,792 kb upper 7/8 0 1 1 0 0 8 thru 31 080000h ? 1fffffh 1,536 kb upper 3/4 0 1 1 0 1 16 thru 31 100000h ? 1fffffh 1 mb upper 1/2 x x 1 1 x none none none none 1 0 0 0 1 0 thru 31 000000h ? 1fefffh 2,044 kb lower 511/512 1 0 0 1 0 0 thru 31 000000h ? 1fdfffh 2,040 kb lower 255/256 1 0 0 1 1 0 thru 31 000000h ? 1fbfffh 2,032 kb lower 127/128 1 0 1 0 x 0 thru 31 000000h ? 1f7fffh 2,016 kb lower 63/64 1 1 0 0 1 0 thru 31 001000h ? 1fffffh 2,044 kb upper 511/512 1 1 0 1 0 0 thru 31 002000h ? 1fffffh 2,040 kb upper 255/256 1 1 0 1 1 0 thru 31 004000h ? 1fffffh 2,032 kb upper 127/128 1 1 1 0 x 0 thru 31 008000h ? 1fffffh 2,016 kb upper 63/64
24 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet notes: 1. data bytes are shifted with most significant bit first. byte fi elds with data in parenthesis ?()? indicate data being read fr om the device on the so pin. 2. the status register contents will repeat continuously until cs# te rminates the instruction. 3. quad page program input data: io0 = (d4, d0, ??) io1 = (d5, d1, ??) io2 = (d6, d2, ??) io3 = (d7, d3, ??) 4. this instruction is recommended when using the dual or quad ?continuous read mode? feature. see section 7.15 and section 7.16 on page 40 for more information. table 7.1 manufacturer identification manufacturer id value (mf7-mf0) efh table 7.2 device identification device density device id instruction value s25fl004k (id7-id0) abh, 90h, 92h, 94h 12h (id15-id0) 9fh 4013h s25fl008k (id7-id0) abh, 90h, 92h, 94h 13h (id15-id0) 9fh 4014h s25fl016k (id7-id0) abh, 90h 14h (id15-id0) 9fh 4015h table 7.3 instruction set (erase, program instructions (1) ) instruction name byte 1 (code) byte 2 byte 3 byte 4 byte 5 byte 6 write enable 06h write enable for volatile status register 50h write disable 04h read status register-1 05h (s7?s0) (2) read status register-2 35h (s15?s8) (2) write status register 01h (s7?s0) (s15?s8) page program 02h a23?a16 a15?a8 a7?a0 (d7?d0) quad page program 32h a23?a16 a15?a8 a7?a0 (d7?d0, ?) (3) sector erase (4 kb) 20h a23?a16 a15?a8 a7?a0 block erase (32 kb) 52h a23?a16 a15?a8 a7?a0 block erase (64 kb) d8h a23?a16 a15?a8 a7?a0 chip erase c7h/60h erase / program suspend 75h erase / program resume 7ah power-down (s25fl004k/s25fl008k) b9h deep power-down (s25fl016k) b9h continuous read mode reset (4) ffh ffh
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 25 data sheet notes: 1. dual output data io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 2. dual input address io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 3. quad output data io0 = (d4, d0, ?..) io1 = (d5, d1, ?..) io2 = (d6, d2, ?..) io3 = (d7, d3, ?..) 4. quad input address set burst with wrap input io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x, x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x, x, x, x, x, x, w6 x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io3 = x, x, x, x, x, x, x, x 5. fast read quad i/o data io0 = (x, x, x, x, d4, d0, ?..) io1 = (x, x, x, x, d5, d1, ?..) io2 = (x, x, x, x, d6, d2, ?..) io3 = (x, x, x, x, d7, d3, ?..) 6. word read quad i/o data io0 = (x, x, d4, d0, ?..) io1 = (x, x, d5, d1, ?..) io2 = (x, x, d6, d2, ?..) io3 = (x, x, d7, d3, ?..) 7. the lowest address bit must be 0. (a0 = 0) 8. the lowest 4 address bits must be 0. (a0, a1, a2, a3 = 0) table 7.4 instruction set (read instructions) instruction name byte 1 (code) byte 2 byte 3 byte 4 byte 5 byte 6 read data 03h a23?a16 a15?a8 a7?a0 (d7?d0) fast read 0bh a23?a16 a15? a8 a7?a0 dummy (d7?d0) fast read dual output 3bh a23?a 16 a15?a8 a7?a0 dummy (d7?d0, ?) (1) fast read quad output 6bh a23?a16 a15?a8 a7?a0 dummy (d7?d0, ?) (3) fast read dual i/o bbh a23?a8 (2) a7?a0, m7?m0 (2) (d7?d0, ?) (1) fast read quad i/o ebh a23?a0, m7?m0 (4) (x,x,x,x, d7?d0, ?) (5) (d7?d0, ?) (3) word read quad i/o (7) e7h a23?a0, m7?m0 (4) (x,x, d7?d0, ?) (6) (d7?d0, ?) (3) octal word read quad i/o (8) e3h a23?a0, m7?m0 (4) (d7?d0, ?) (3) set burst with wrap 77h xxxxxx, w6?w4 (4)
26 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet notes: 1. the device id will repeat continuously until cs# terminates the instruction. 2. see manufacturer and device identification table for device id information. 3. security register address: security register 1: a23-16 = 00h; a15-8 = 10h; a7-0 = byte address security register 2: a23-16 = 00h; a15-8 = 20h; a7-0 = byte address security register 3: a23-16 = 00h; a15-8 = 30h; a7-0 = byte address 7.1 write enable (06h) the write enable instruction ( figure 7.1 ) sets the write enable latch (wel) bi t in the status register to a 1. the wel bit must be set prior to every page program, q uad page program, sector erase, block erase, chip erase, write status regist er and erase/program securi ty registers instruction. the write enable instruction is entered by driving cs# low, shifting the instruction code ?06h? into the data inpu t (si) pin on the rising edge of clk, and then driving cs# high. figure 7.1 write enable instruction sequence diagram table 7.5 instruction set (id, security instructions) instruction name byte 1 (code) byte 2 byte 3 byte 4 byte 5 byte 6 release power down / device id (s25fl004k/s25fl008k) abh dummy dummy dummy (id7-id0) (1) release from deep power down / device id (s25fl016k) abh dummy dummy dummy (id7-id0) (1) manufacturer/ device id (2) 90h dummy dummy 00h (mf7-mf0) (id7-id0) manufacturer/device id by dual i/o 92h a23-a8 a7-a0, m[7:0] (mf[7:0], id[7:0]) manufacture/device id by quad i/o 94h a23-a0, m[7:0] xxxx, (mf[7:0], id[7:0]) (mf[7:0], id[7:0], ?) jedec id 9fh (mf7-mf0) manufacturer (id15-id8) memory type (id7-id0) capacity read unique id 4bh dummy dummy dummy dummy (id63-id0) read sfdp register 48h, 5ah 00h 00h a7-a0 dummy (d7-0) erase security registers (3) 44h a23-a16 a15-a8 a7-a0 program security registers (3) 42h a23-a16 a15-a8 a7-a0 (d7-0) (d7-0) read security registers (3) 48h a23-a16 a15-a8 a7-a0 dummy (d7-0) in s tr u ction (06h) c s # clk s i s o high imped a nce mode 3 mode 0 0 1 2 3 4 5 6 7 mode 3 mode 0
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 27 data sheet 7.2 write enable for volatile status register (50h) the non-volatile status re gister bits described in section 6.1, status register on page 16 can also be written to as volatile bits. this gives more flexibility to change the system configur ation and memory protection schemes quickly without waiting for t he typical non-volatile bit write cycl es or affecting th e endurance of the status register non-volatile bits. to write the volatile values into the stat us register bits, the write enable for volatile status register (50h) instru ction must be issued prior to a write status register ( 01h) instruction. write enable for volatile status register instruction ( figure 7.2 ) will not set the write enable latch (wel) bit, it is only valid for the write status register instruct ion to change the volatile st atus register bit values. figure 7.2 write enable for volatile status register instruct ion sequence diagram 7.3 write disable (04h) the write disable instruction (figure 6) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving cs# low, shifting the instruction code ?04h? into the si pin and then driving cs# high. note that the wel bit is automatically reset after power-up and upon completion of the write status register, erase/pr ogram security registers, page pr ogram, quad page program, sector erase, block erase and chip erase instructions. figure 7.3 write disable instruction sequence diagram in s tr u ction (50h) c s # clk s i s o high imped a nce mode 3 mode 0 0 1 2 3 4 5 6 7 mode 3 mode 0 in s tr u ction (04h) c s # clk s i s o high imped a nce mode 3 mode 0 0 1 2 3 4 5 6 7 mode 3 mode 0
28 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.4 read status register-1 (05h) a nd read status register-2 (35h) the read status register instructions allow the 8-bit status registers to be read. the instruction is entered by driving cs# low and shifting the in struction code ?05h? for st atus register-1 or ?35h ? for status register-2 into the si pin on the rising edge of cl k. the status register bits are then shifted out on the so pin at the falling edge of clk with most signifi cant bit (msb) fi rst as shown in figure 7.4 . the status register bits are shown in figure 6.1 and figure 6.2 and include the busy, wel, bp2-bp0, tb, sec, srp0, srp1, qe, lb3-1, cmp and sus bits (see section 6.1, status register on page 16 ). the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instructio n. the status register c an be read continuously, as shown in figure 7.4 . the instruction is completed by driving cs# high. figure 7.4 read status register in struction sequence diagram 7.5 write status register (01h) the write status register instruction allows the status register to be written. only non-volatile status register bits srp0, sec, tb, bp2, bp1, bp0 (bits 7 thru 2 of status register-1) and cmp, lb3, lb2, lb1, qe, srp1 (bits 14 thru 8 of status register-2) can be written to. all other status register bit locations are read-only and will not be affe cted by the write status r egister instruction. lb3-1 are non-volatile otp bits; once each is set to 1, it can not be cleared to 0. the status regist er bits are shown in figure 6.1 and figure 6.2 on page 18 , and described section 6.1, status register on page 16 . to write non-volatile st atus register bits, a standar d write enable (06h) instruct ion must previously have been executed for the device to accept the write status register instruct ion (status register bit wel must equal 1). once write enabled, the instruction is enter ed by driving cs# low, sending the instruction code ?01h?, and then writi ng the status register data byte as illustrated in figure 7.5 . to write volatile status r egister bits, a write enable for volatile st atus register (50h) instruction must have been executed prior to the write status register inst ruction (status register bit wel remains 0). however, srp1 and lb3, lb2, lb1 can not be changed from 1 to 0 because of the otp prot ection for these bits. upon power off, the volatile status register bit values will be lost , and the non-volatile status register bit values will be restored when power on again. to complete the write status regist er instruction, the cs # pin must be driven hi gh after the eighth or sixteenth bit of data t hat is clocked in. if this is not done the wr ite status register in struction will not be executed. if cs# is driven high afte r the eighth clock the cmp, qe and srp1 bits will be cleared to 0. during non-volatile status register write operation (06h combined with 0 1h), after cs# is driven high, the self-timed write status r egister cycle will commence for a time duration of t w (see section 8.6, ac electrical characteristics on page 64 ). while the write status register cycle is in progress, the re ad status register instruction may still be accessed to check the status of the busy bit. the busy bi t is a 1 during the write status register cycle and a 0 when the cycle is finished and ready to acc ept other instructions again. after the write status register cy cle has finished, the write enable latch (wel) bit in th e status register will be cleared to 0. in s tr u ction (05h or 3 5h) c s # clk s i s o high imped a nce s t a t us regi s ter 1 or 2 o u t 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 mode 3 mode 0 = m s b s t a t us regi s ter 1 or 2 o u t 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 29 data sheet during volatile status register wr ite operation (50h combined with 01h), after cs# is driven high, the status register bits will be refr eshed to the new values wi thin the time period of t shsl2 (see section 8.6, ac electrical characteristics on page 64 ). busy bit will remain 0 during the status register bit refresh period. refer to section 6.1, status register on page 16 for detailed status register bi t descriptions. factory default for all status register bits are 0. figure 7.5 write status register in struction sequence diagram 7.6 read data (03h) the read data instruction allows one or more data bytes to be sequentially read from the memory. the instruction is initiated by driving the cs# pin low and then shifting the instruction code ?03h? followed by a 24-bit address (a23-a0) into the si pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memo ry location will be shifted out on the so pin at the falling edge of clk with most signifi cant bit (msb) first. t he address is automatically incremented to the next higher address after each byte of da ta is shifted out allowing for a continuous stream of data. this means that the entire memory can be a ccessed with a single instruction as long as the clock continues. the instruction is completed by driving cs# high. the read data instruction sequence is shown in figure 7.6 . if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read data instruction allows clock rates from dc to a maximum of f r . ( see ac electrical characteristics on page 64. ) figure 7.6 read data instruction sequence diagram c s # clk s i s o = m s b 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 mode 3 mode 0 in s tr u ction (01h) high imped a nce s t a t us regi s ter in mode 3 mode 0 7 6 5 4 3 2 1 0 x 14 1 3 12 11 x 9 8 c s # clk s i s o = m s b mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 in s tr u ction (0 3 h) high imped a nce 24-bit addre ss d a t a o u t 2 d a t a o u t 1 7 6 5 4 3 2 1 0 7 2 3 22 21 3 2 1 0
30 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.7 fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possible frequency of f r . ( see ac electrical characteristics on page 64. ) this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 7.7 . the dummy clocks allow the devices internal circuits additional time for setting up the initial address. during the dummy clocks the data value on the so pin is a ?don?t care?. figure 7.7 fast read instruction sequence diagram = m s b c s # clk s i s o mode 3 mode 0 in s tr u ction (0bh) 24-bit addre ss 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 2 3 22 21 3 2 1 0 c s # clk s i s o 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 d u mmy byte d a t a o u t 2 d a t a o u t 1 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 31 data sheet 7.8 fast read dual output (3bh) the fast read dual output (3bh) instruction is similar to the standard fast read (0bh ) instruction except that data is output on two pins; io0 and io1. this allo ws data to be transferred from the s25fl004k/s25fl008k/ s25fl016k at twice the rate of standard spi devices. th e fast read dual output instruction is ideal for quickly downloading code from flash to ram upon power- up or for applications t hat cache code-segments to ram for execution. similar to the fast read instruction, the fast read dual output inst ruction can operate at the highest possible frequency of f r . ( see ac electrical characteristics on page 64. ) this is accomplished by adding eight ?dummy? clocks after the 24-bit address as shown in figure 7.8 . the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input dat a during the dummy clocks is ?don?t care?. however, the io0 pin s hould be high-impedance prior to t he falling edge of the first data out clock. figure 7.8 fast read dual output instruction sequence diagram c s clk io0 io1 mode 3 mode 0 in s tr u ction ( 3 bh) 24-bit addre ss 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 2 3 22 21 3 2 1 0 c s clk io0 io1 = m s b d a t a o u t 2 d a t a o u t 1 d a t a o u t 4 d a t a o u t 3 d u mmy clock s io_0 s witche s from inp u t to o u tp u t 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 4 8 49 50 51 52 5 3 54 55 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 6
32 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.9 fast read quad output (6bh) the fast read quad output (6bh) instruction is similar to the fast read dual out put (3bh) instruction except that data is output on four pins, io0, io1, io2, and io3. a quad enable of status register-2 must be executed before the device will accept the fast read quad output instruction (statu s register bit qe must equal 1). the fast read quad output instruction allows data to be transferred from the s25fl004k/s25fl008k/ s25fl016k at four times the ra te of standard spi devices. the fast read quad output instruction can o perate at the highest possible frequency of fr. ( see ac electrical characteristics on page 64. ) this is accomplished by adding ei ght ?dummy? clocks after the 24-bit address as shown in figure 7.9 . the dummy clocks allow the device's in ternal circuits add itional time for setting up the initial address. the i nput data during the dummy clocks is ? don?t care?. however, the io pins should be high-impedance prior to the falling edge of the first data out clock. figure 7.9 fast read quad output in struction sequence diagram c s clk io0 io1 io2 io 3 in s tr u ction (6bh) 24-bit addre ss 2 3 22 21 3 2 1 0 c s clk io0 io1 io2 io 3 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 d u mmy clock s io_0 s witche s from inp u t to o u tp u t 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 byte 1 byte 2 byte 3 byte 4 mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 33 data sheet 7.10 fast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io0 and io1. it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23-0) two bits per clock. this reduced instruction overhead may allow for code execution (xip) directly from the dual spi in some applications. fast read dual i/o with ?continuous read mode? the fast read dual i/o instruction can further reduc e instruction overhead through setting the ?continuous read mode? bits (m7-0) after the inpu t address bits (a23-0), as shown in figure 7.10 . the upper nibble of the (m7-4) controls the length of the next fast read dual i/o instructi on through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3-0) are don?t care (?x?). ho wever, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5-4 = (1,0), then t he next fast read dual i/o instruction (after cs# is raised and then lowered) does not require the bbh instru ction code, as shown in figure 7.11 . this reduces the instruction sequence by eight clocks and allows t he read address to be immediat ely entered after cs# is asserted low. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next instruction (after cs# is raised and then lowered) requi res the first byte instruction code, t hus returning to normal operation. a ?continuous read mode? reset instruction can also be used to reset (m7-0) before issuing normal instructions. ( see continuous read mode reset (ffh or ffffh) on page 40. ) figure 7.10 fast read dual i/o instruction sequence (i nitial instruction or previous m5-4 ? 10) c s # clk io0 io1 in s tr u ction (bbh) 6 4 2 0 6 4 2 0 6 4 2 0 6 4 7 5 3 1 7 5 3 1 7 5 3 1 a2 3 -16 a15- 8 a7-0 m7-0 7 5 c s # clk io0 io1 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 io s witche s from inp u t to o u tp u t byte 1 byte 2 byte 3 byte 4 2 3 24 25 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 mode 3 mode 0 mode 3 mode 0
34 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet figure 7.11 fast read dual i/o instruction sequence (previous instruction set m5-4 = 10) 7.11 fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh ) instruction except that address and data bits are input and output through four pins io0, io1, io2 and io3 and four dummy clock are required prior to the data output. the quad i/o dramat ically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad enable bit (qe) of status register-2 must be set to enable t he fast read quad i/o instruction. fast read quad i/o with ?continuous read mode? the fast read quad i/o instructi on can further reduce instruction ov erhead through setting the ?continuous read mode? bits (m7-0) after the inpu t address bits (a23-0), as shown in figure 7.12, fast read quad i/o instruction sequence (initial instruct ion or previous m5-4 110) on page 35 . the upper nibble of the (m7-4) controls the length of the next fast read quad i/o inst ruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3- 0) are don?t care (?x?). howe ver, the io pins should be high-impedance prior to the falling edge of the fi rst data out clock. if the ?continuous read mode? bits m5-4 = (1,0), then t he next fast read quad i/o instruction (after cs# is raised and then lowered) does not require the ebh instru ction code, as shown in figure 7.13, fast read quad i/o instruction sequence (previous instruction set m5-4 = 10) on page 35 . this reduces the instruction sequence by eight clocks and allows the read address to be immediately entered after cs# is asserted low. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next instruction (after cs# is raised and then lowered) requires the first byte instruction code, thus returning to normal operation. a ?continuous read mode? reset instruction can also be used to rese t (m7-0) before issuing normal instructions (see section 7.16, continuous read mode reset (ffh or ffffh) on page 40 ). c s # clk io0 io1 mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 6 4 2 0 6 4 2 0 6 4 2 0 6 4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 a2 3 -16 a15- 8 a7-0 m7-0 c s # clk io0 io1 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 15 16 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 io s witche s from inp u t to o u tp u t byte 1 byte 2 byte 3 byte 4 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 35 data sheet figure 7.12 fast read quad i/o instruction sequence (initial instruction or previous m5-4 ? 10) figure 7.13 fast read quad i/o instruction sequence (previous instruction set m5-4 = 10) fast read quad i/o with ?8/16/32/64-byte wrap around? the fast read quad i/o instruction can also be used to access a specific portion within a page by issuing a ?set burst with wrap? command prior to ebh. the ?s et burst with wrap? comm and can either enable or disable the ?wrap around? feature for the following ebh comm ands. when ?wrap around? is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. the output data starts at the initial address s pecified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte secti on, the output will wrap around to the b eginning boundary automatic ally until cs# is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a crit ical address and then fill the cache afterwards within a fixed length (8/16/32/64- byte) of data without issuing multiple read commands. the ?set burst with wrap? instruction allows three ?wra p bits?, w6-4 to be set. the w4 bit is used to enable or disable the ?wrap around? operation while w6-5 are used to spec ify the length of the wrap around section within a page. see section 7.14, set burst with wrap (77h) on page 39 . c s # clk io0 io1 io2 io 3 mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 io s witche s from inp u t to o u tp u t in s tr u ction (ebh) 4 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 3 7 a2 3 -16 a15- 8 a7-0 m7-0 byte 1 byte 2 d u mmy d u mmy c s # clk io0 io1 io2 io 3 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 mode 3 mode 0 io s witche s from inp u t to o u tp u t 4 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 3 7 a2 3 -16 a15- 8 a7-0 m7-0 byte 1 byte 2 d u mmy d u mmy
36 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.12 word read quad i/o (e7h) the word read quad i/o (e7h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lowest address bit (a0) must equal 0 and only two dummy clock are required prior to the data output. the quad i/o dramatically reduces instruction overhead a llowing faster random access for code execution (xip) directly from the quad spi. the quad enable bit (qe) of status register-2 must be set to enable the word read quad i/o instruction. word read quad i/o with ?continuous read mode? the word read quad i/o instruction can further redu ce instruction overhead th rough setting the ?continuous read mode? bits (m7-0) after the inpu t address bits (a23-0), as shown in figure 7.14 . the upper nibble of the (m7-4) controls the l ength of the next fast read quad i/o instruct ion through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3-0) are don?t care (?x?). ho wever, the io pins should be high-impedance prior to the falling edge of the first data out clock. if the ?continuous read mode? bits m5-4 = (1,0), then t he next fast read quad i/o instruction (after cs# is raised and then lowered) does not require the e7h instru ction code, as shown in figure 7.15 . this reduces the instruction sequence by eight clocks and allows t he read address to be immediat ely entered after cs# is asserted low. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next instruction (after cs# is raised and then lowered) requi res the first byte instruction code, t hus returning to normal operation. a ?continuous read mode? reset instruction can also be used to reset (m7-0) before issuing normal instructions (see section 7.16, continuous read mode reset (ffh or ffffh) on page 40 ). figure 7.14 word read quad i/o instruction sequence (i nitial instruction or previous m5-4 ? 10) c s # clk io0 io1 io2 io 3 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 mode 3 mode 0 16 17 1 8 19 20 21 22 2 3 io s witche s from inp u t to o u tp u t in s tr u ction (e7h) 4 0 4 0 4 0 4 0 4 0 4 0 4 4 0 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 a2 3 -16 a15- 8 a7-0 m7-0 byte 1 byte 2 d u mmy byte 3
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 37 data sheet figure 7.15 word read quad i/o instruction sequence (previous instruction set m5-4 = 10) word read quad i/o with ?8/16/32/64-byte wrap around? the word read quad i/o instruction can also be used to access a specific portion within a page by issuing a ?set burst with wrap? command prior to e7h. the ?set burst with wrap? co mmand can either enable or disable the ?wrap around? feature for the following e7h command s. when ?wrap around? is enabled, the data being accessed can be limited to either a 8, 16, 32 or 64-byte section of a 256-byte page. the output data starts at the initial address s pecified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte secti on, the output will wrap around to the b eginning boundary automatic ally until cs# is pulled high to terminate the command. the burst with wrap feature allows applications that use cache to quickly fetch a crit ical address and then fill the cache afterwards within a fixed length (8/16/32/64- byte) of data without issuing multiple read commands. the ?set burst with wrap? instruction allows three ?wra p bits?, w6-4 to be set. the w4 bit is used to enable or disable the ?wrap around? operation while w6-5 are used to spec ify the length of the wrap around section within a page. see section 7.14, set burst with wrap (77h) on page 39 . 7.13 octal word read quad i/o (e3h) the octal word read quad i/o (e3h) instruction is similar to the fast read quad i/o (ebh) instruction except that the lower four address bits (a0, a1, a2, a3) must equal 0. as a result, the dummy clocks are not required, which further reduces the instruction over head allowing even faster random access for code execution (xip). the quad enable bit (qe) of status register-2 must be set to enable the octal word read quad i/o instruction. octal word read quad i/o with ?continuous read mode? the octal word read quad i/o instruction can furt her reduce instruction ov erhead through setting the ?continuous read mode? bits (m7-0) after t he input address bits (a23-0), as shown in figure 7.16, octal word read quad i/o instruction sequence (initial instruction or previous m5-4 1 10) on page 38 . the upper nibble of the (m7-4) controls the length of t he next octal word read quad i/o instruction through the inclusion or exclusion of the first byte instruction code. the lower nibble bits of the (m3-0) are don?t care (?x?). however, the io pins should be high-impedance prio r to the falling edge of the first data out clock. if the ?continuous read mode? bits m5-4 = (1,0), then t he next fast read quad i/o instruction (after cs# is raised and then lowered) does not require the e3h instru ction code, as shown in figure 7.17, octal word read quad i/o instruction sequence (previous instruction set m5-4 = 10) on page 38 . this reduces the instruction sequence by eight clocks and allows the read address to be immedi ately entered after cs# is asserted low. if the ?continuous read mode? bits m5-4 do not equal to (1,0), the next instruction (after cs# is raised and then lowered) requi res the first byte instruction code, t hus returning to normal operation. a ?continuous read mode? reset instruction can also be used to reset (m7-0) before issuing normal instructions (see section 7.16, continuous read mode reset (ffh or ffffh) on page 40 ). c s # clk io0 io1 io2 io 3 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 mode 3 mode 0 io s witche s from inp u t to o u tp u t 4 0 4 0 4 0 4 0 4 0 4 0 4 4 0 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 a2 3 -16 a15- 8 a7-0 m7-0 byte 1 byte 2 d u mmy byte 3
38 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet figure 7.16 octal word read quad i/o instruction sequenc e (initial instructi on or previous m5-4 ? 10) figure 7.17 octal word read quad i/o instruction sequence (previous instruction set m5-4 = 10) c s # clk io0 io1 io2 io 3 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 mode 3 mode 0 io s witche s from inp u t to o u tp u t in s tr u ction (e 3 h) 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 a2 3 -16 a15- 8 a7-0 m7-0 byte 1 byte 2 d u mmy byte 3 c s # clk io0 io1 io2 io 3 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 mode 3 mode 0 io s witche s from inp u t to o u tp u t 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 a2 3 -16 a15- 8 a7-0 m7-0 byte 1 byte 2 byte 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 byte 4
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 39 data sheet 7.14 set burst with wrap (77h) the set burst with wrap (77h) instruction is used in conjunction with ?fast read quad i/o? and ?word read quad i/o? instructions to access a fi xed length of 8/16/32/64-byte sectio n within a 256-byte page. certain applications can benefit from this feature and improve the overall system code execution performance. similar to a quad i/o instruction, the set burst with wr ap instruction is initiated by driving the cs# pin low and then shifting the instruction code ?77h ? followed by 24 dummy bits and 8 ?wrap bits?, w7-0. the instruction sequence is shown in figure 7.18, set burst with wrap instruction sequence on page 39 . wrap bit w7 and the lower nibble w3-0 are not used. once w6-4 is set by a set burst with wrap instruction, all the following ?fast read quad i/o? and ?word read quad i/o? instructions will use the w6-4 setting to access the 8/16/32/64-byte section within any page. to exit the ?wrap around? function and return to normal read operation, anot her set burst with wrap instruction should be issued to set w4 = 1. the default value of w4 upon power on is 1. in the case of a system reset while w4 = 0, it is recommended that the c ontroller issues a set burs t with wrap instruction to reset w4 = 1 prior to any normal read instructions since s25fl004k/s25fl008k/s25fl016k does not have a hardware reset pin. figure 7.18 set burst with wrap instruction sequence 7.15 continuous read mode bits (m7-0) the ?continuous read mode? bits are used in conjuncti on with ?fast read dual i/ o?, ?fast read quad i/o?, ?word read quad i/o? and ?octal word read quad i/o? instructions to provid e the highest random flash memory access rate with minimum spi instruction ov erhead, thus allow true xip (execute in place) to be performed on serial flash devices. m7-0 need to be set by the dual/quad i/o read instruct ions. m5-4 are used to cont rol whether the 8-bit spi instruction code (bbh, ebh, e7h or e3h) is needed or not for the next command. when m5-4 = (1,0), the next command will be treated same as the current d ual/quad i/o read command wi thout needing the 8-bit instruction code; when m5-4 do not equal to (1,0), t he device returns to normal spi mode, all commands can be accepted. m7-6 and m3-0 are reserved bits for future use, either 0 or 1 values can be used. w6, w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap around wrap length 0 0 yes 8-byte no n/a 0 1 yes 16-byte no n/a 1 0 yes 32-byte no n/a 1 1 yes 64-byte no n/a c s # clk io0 io1 io2 io 3 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 mode 3 mode 0 in s tr u ction (77h) x x x x x x w4 x x x x x x x w5 x x x x x x x w6 x x x x x x x x x don ? t c a re don ? t c a re don ? t c a re wr a p b it
40 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.16 continuous read m ode reset (ffh or ffffh) continuous read mode re set instruction can be used to set m4 = 1, thus the device will release the continuous read mode and return to normal spi operation, as shown in figure 7.19 . figure 7.19 continuous read mode reset for fast read dual/quad i/o since s25fl004k/s25fl008k/s25fl016k does not have a har dware reset pin, so if the controller resets while s25fl004k/s25fl008k/s25fl016k is set to continuous mode read, the s25fl004k/s25fl008k/ s25fl016k will not recognize any initial standard spi in structions from the controller. to address this possibility, it is recommended to issue a continuous read mode reset instruction as the first instruction after a system reset. doing so will release the device fr om the continuous read mo de and allow standard spi instructions to be recognized. to reset ?continuous read mode? during quad i/o operat ion, only eight clocks are needed. the instruction is ?ffh?. to reset ?continuous read mode? during dual i/ o operation, sixteen clocks are needed to shift in instruction ?ffffh?. c s # clk io0 io1 io2 io 3 mode 3 mode 0 don ? t c a re mode 3 mode 0 don ? t c a re don ? t c a re 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 mode bit re s et for q ua d i/o mode bit re s et for q ua d i/o ffh ffh
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 41 data sheet 7.17 page program (02h) the page program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write enab le instruction must be executed before the device will accept the page program instruction (status register bit wel= 1). the instruction is initiated by driving the cs# pin low then shifting the instruction code ?02h? followed by a 24-bit address (a23-a0) and at least one data byte, into the si pin. the cs# pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 7.20, page program instruction sequence diagram on page 41 . if an entire 256-byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the last address byte is not 0, and the number of clocks exceed the remaining page length, the addressi ng will wrap to the beginning of the page. in so me cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes with in the same page. one condition to perform a partial page program is that the number of clocks can not exceed t he remaining page length. if more than 256 bytes are sent to the device the addres sing will wrap to the beginning of the page and overwrite previously sent data. as with the write and erase instructio ns, the cs# pin must be driven high afte r the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after cs# is driven high, the self-timed p age program instruction will comme nce for a time duration of t pp . ( see ac electrical characteristics on page 64. ) while the page program cycle is in progress, the read status register instruction may still be accessed for checking the stat us of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is fi nished and the device is ready to accept other instructions again. after the page progr am cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the page pr ogram instruction will not be execut ed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits. figure 7.20 page program instru ction sequence diagram c s # clk mode 3 mode 0 c s # clk s i in s tr u ction (02h) 24-bit addre ss d a t a byte 1 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 2 3 22 21 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 s i 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 = m s b
42 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.18 quad page program (32h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io0, io1, io2, and io3. the quad page program can improve performance for prom programmer and applications that have slow cloc k speeds <5 mhz. systems with faster clock speed will not realize much benefit for the q uad page program instruct ion since the inherent page program time is much greater than the time it ta ke to clock-in the data. to use quad page program the quad enable in status register-2 must be set (qe=1). a write enable instruction must be executed before the device will accept the quad page program instruction (status register-1, wel=1). the inst ruction is initiated by dr iving the cs# pin low then shifting the instruction code ?32h? followed by a 24-bit address (a23- a0) and at least one data byte, into the io pins. the cs# pin must be held low for the entire length of the instruction whil e data is being sent to the de vice. all other functions of quad page program are identical to standard page prog ram. the quad page program instruction sequence is shown in figure 7.21, quad page program instruction sequence diagram on page 42 . figure 7.21 quad page program instruction sequence diagram c s # clk io0 io1 io2 io 3 mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 in s tr u ction ( 3 2h) 24-bit addre ss byte 1 byte 2 byte 3 byte 4 2 3 22 21 3 2 1 0 4 0 4 0 4 0 4 0 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 40 41 42 4 3 44 45 46 47 4 8 49 50 51 52 5 3 54 55 5 3 6 5 3 7 5 38 5 3 9 540 541 542 54 3 mode 3 mode 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 byte 5 byte 6 byte 7 byte 8 byte 9 byte 10 byte 11 byte 12 byte 25 3 byte 254 byte 255 byte 256 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 clk io0 io1 io2 io 3 c s # = m s b
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 43 data sheet 7.19 sector erase (20h) the sector erase instruction sets all memory within a s pecified sector (4k-bytes) to the erased state of all 1s (ffh). a write enable instruction mu st be executed before the device will ac cept the sector erase instruction (status register bit wel must equal 1) . the instruction is initiated by dr iving the cs# pin low and shifting the instruction code ?20h? followed a 24- bit sector addre ss (a23-a0). (see section 1., block diagrams on page 9 for the block diagrams of s25fl004k, s25fl008k, and s25fl016k.) the sector erase instruction sequence is shown in figure 7.22 on page 43 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the sector erase instruction will not be executed. after cs# is driven high, t he self-timed sector erase instruction will commence for a time duration of t se . ( see ac electrical characteristics on page 64. ) while the sector erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sect or erase cycle and becomes a 0 when the cycle is finished and the device is ready to ac cept other instructions again. after the sector erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be executed if the addressed sector is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see table 6.2 , table 6.3 , and table 6.4 for status register memo ry protection (cmp = 0)). figure 7.22 sector erase instruct ion sequence diagram c s # clk mode 3 mode 0 mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 29 3 0 3 1 in s tr u ction (20h) 24-bit addre ss 2 3 22 2 1 0 high imped a nce s io s o = m s b
44 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.20 32 kb block erase (52h) the block erase instruction sets all me mory within a specified block (32k-b ytes) to the erased state of all 1s (ffh). a write enable instruction must be executed befo re the device will accept the block erase instruction (status register bit wel must equal 1) . the instruction is initiated by dr iving the cs# pin low and shifting the instruction code ?52h? followed a 24-bit block address (a23-a0). (see section 1., block diagrams on page 9 for the block diagrams of s25fl004k, s25fl008k,and s25fl016k.) the block erase instruction sequence is shown in figure 7.23 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be ex ecuted. after cs# is driven high, t he self-timed block erase instruction will commence for a time duration of t be1 . ( see ac electrical char acteristics on page 64. ) while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the bloc k erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed sector is prot ected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see table 6.2 , table 6.3 , and table 6.4 for status register memory protection (cmp = 0)). figure 7.23 32 kb block erase instruction sequence diagram c s # clk mode 3 mode 0 mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 29 3 0 3 1 in s tr u ction (52h) 24-bit addre ss 2 3 22 2 1 0 high imped a nce s io s o = m s b
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 45 data sheet 7.21 64 kb block erase (d8h) the block erase instruction sets all me mory within a specified block (64k-b ytes) to the erased state of all 1s (ffh). a write enable instruction must be executed befo re the device will accept the block erase instruction (status register bit wel must equal 1) . the instruction is initiated by dr iving the cs# pin low and shifting the instruction code ?d8h? followed a 24-bit block address (a23-a0). (see section 1., block diagrams on page 9 for the block diagrams of s25fl004k, s25fl008k,and s25fl016k.) the block erase instruction sequence is shown in figure 7.24 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be ex ecuted. after cs# is driven high, t he self-timed block erase instruction will commence for a time duration of t be . ( see ac electrical characteristics on page 64. ) while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the bloc k erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed sector is prot ected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see table 6.2 , table 6.3 , and table 6.4 for status register memory protection (cmp = 0)). figure 7.24 64 kb block erase instruction sequence diagram mode 3 mode 0 mode 3 mode 0 c s # clk s i s o = m s b in s tr u ction (d 8 h) 24-bit addre ss high imped a nce 2 3 22 2 1 0 0 1 2 3 4 5 6 7 8 9 29 3 0 3 1
46 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.22 chip erase (c7h / 60h) the chip erase instruction sets all me mory within the device to the eras ed state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by dr iving the cs# pin low and sh ifting the instruction code ?c7h? or ?60h?. the chip erase instruction sequence is shown in figure 7.25 . the cs# pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after cs# is driven hi gh, the self-timed chip erase instruction will commence for a time duration of t ce . ( see ac electrical characteristics on page 64. ) while the chip erase cycle is in progress, the read status regi ster instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other instructions again. after the chip erase cycle has finished the write enabl e latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be exec uted if any page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits (see table 6.2 , table 6.3 , and table 6.4 for status register memory pr otection (cmp = 0)). figure 7.25 chip erase instruction sequence diagram mode 3 mode 0 mode 3 mode 0 c s # clk s i s o in s tr u ction (c7h/60h) high imped a nce 0 1 2 3 4 5 6 7
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 47 data sheet 7.23 erase / program suspend (75h) the erase/program suspend inst ruction 75h, allows the system to inte rrupt a sector or block erase operation or a page program oper ation and then read from or pr ogram/erase data to, any other sectors or blocks. the erase/program suspend instru ction sequence is shown in figure 7.26, erase/program suspend instruction sequence on page 47 . the write status register instruction (01h) and erase instructions (20h, 52h, d 8h, c7h, 60h, 44h) are not allowed during erase suspend. erase suspend is valid only during the sector or block erase operation. if written during the chip erase operation, the erase suspend instruct ion is ignored. the wr ite status register instruction (01h) and program instru ctions (02h, 32h, 42 h) are not allowed during program suspend. program suspend is valid only during the page program or quad page program operation. the erase/program suspend instruction 75h will be accept ed by the device only if t he sus bit in the status register equals to 0 and the busy bi t equals to 1 while a sector or block erase or a page program operation is on-going. if the sus bit equals to 1 or the busy bit equals to 0, the su spend instruction will be ignored by the device. a maximum of time of t sus ( section 8.6, ac electrical characteristics on page 64 ) is required to suspend the erase or program operation. the busy bit in the status register will be cleared from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately after erase/program suspend. for a previously resumed eras e/program operation, it is also required that the suspend instruction 75h is not issued earlier than a minimum of time of t sus following the preceding resume instruction 7ah. unexpected power off during the erase/program susp end state will reset the device and release the suspend state. sus bit in the status register will al so reset to 0. the data within the page, se ctor or block that was being suspended may become corrupted. it is recomm ended for the user to implement system design techniques against the accidental pow er interruption and preserve data integrity during erase/program suspend state. figure 7.26 erase/program suspend instruction sequence c s # clk s i s o in s tr u ction (75h) high imped a nce mode 3 mode 0 mode 3 mode 0 0 1 2 3 4 5 6 7 accept re a d or progr a m in s tr u ction t s u s
48 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.24 erase / program resume (7ah) the erase/program resume instruction ?7ah? must be wr itten to resume the sector or block erase operation or the page program operat ion after an erase/program suspend. the resume instruction ?7ah? will be accepted by the device only if the sus bit in the stat us register equals to 1 and the busy bit equals to 0. after issued the sus bit will be cleared from 1 to 0 imme diately, the busy bit will be set from 0 to 1 within 200 ns and the sector or block w ill complete the erase operation or the page will comple te the program operation. if the sus bi t equals to 0 or the busy bit equals to 1, the resume instruction ?7ah? will be ignored by the device. the erase/program resu me instruction sequence is shown in figure 7.27 . resume instruction is ignored if the previous eras e/program suspend operati on was interrupted by unexpected power off. it is also r equired that a subsequent erase/progr am suspend instruction not to be issued within a minimum of time of ?t sus ? following a previous resume instruction. figure 7.27 erase/program resume instruction sequence c s # clk s i in s tr u ction (7ah) mode 3 mode 0 0 1 2 3 4 5 6 7 re su me s ector or block er as e mode 3 mode 0
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 49 data sheet 7.25 deep power-down (b9h) although the standby current dur ing normal operation is relatively low, standby current can be further reduced with the deep power-down instruction. the lowe r power consumption makes the deep power-down instruction especially useful for bat tery powered applications (see i cc1 and i cc2 in section 8.4, dc electrical characteristics on page 63 ). the instruction is initia ted by driving the cs# pin lo w and shifting the instruction code ?b9h? as shown in figure 7.28 . the cs# pin must be driven high after the eighth bit has been latched. if this is not done the deep power- down instruction will not be executed. after cs# is driv en high, the power-down stat e will entered within the time duration of t dp . ( see ac electrical characteristics on page 64. ) while in the power-down state only the release from deep power-down / device id instruction, which restores the device to normal operation, will be recognized. all other instructions ar e ignored. this includes the read stat us register instruction, which is always available during normal oper ation. ignoring al l but one instruction makes the power down state a useful condition for securing maximu m write protection. the device always powers-up in the normal operation with the standby current of i cc1 . figure 7.28 deep power-down instruction sequence diagram c s # clk s i mode 3 mode 0 mode 3 mode 0 0 1 2 3 4 5 6 7 t dp in s tr u ction (b9h) s t a nd a rd c u rrent deep power-down c u rrent
50 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.26 release from deep power-down / device id (abh) the release from deep power-down / device id instructio n is a multi-purpose instruction. it can be used to release the device from the deep po wer-down state, or obtain the devi ces electronic ident ification (id) number. to release the device from the deep po wer-down state, the inst ruction is issued by dr iving the cs# pin low, shifting the instruction code ?abh? and driving cs# high as shown in figure 7.29 . release from deep power- down will take the time duration of t res1 ( section 8.6, ac electrical characteristics on page 64 ) before the device will resume normal operation and other instruct ions are accepted. the cs# pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the deep power-down state, the instruction is initiated by driving the cs# pin low and shifting th e instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first. the device id values for the s25fl004k/s25fl008k/s25fl016k is listed in manufactu rer and device identificat ion table. the device id can be read continuously. the instru ction is completed by driving cs# high. when used to release the device from the deep power-dow n state and obtain the device id, the instruction is the same as previously described, and shown in figure 7.30 , except that after cs# is driven high it must remain high for a time duration of t res2 . after this time duration the dev ice will resume normal operation and other instructions will be accepted. if the release from deep power-down / device id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 7.29 release from deep power-down instruction sequence figure 7.30 release from deep power-down / devi ce id instruction sequence diagram c s # clk s i s o in s tr u ction (abh) high imped a nce mode 3 mode 0 mode 3 mode 0 0 1 2 3 4 5 6 7 s t a nd- b y c u rrent t re s 1 deep power-down c u rrent c s # clk s i s o in s tr u ction (abh) high imped a nce mode 3 mode 0 mode 3 mode 0 3 d u mmy byte s t re s 2 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 = m s b 2 3 22 21 3 2 1 0 7 6 5 4 3 2 1 0 device id deep power-down c u rrent s t a nd- b y c u rrent
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 51 data sheet 7.27 read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the releas e from deep power-down / device id instruction that provides both the jedec assigned manufa cturer id and the specific device id. the read manufacturer/device id instruction is very si milar to the release from deep power-down / device id instruction. the instruction is initiated by driving the cs# pin low and shifting the instruction code ?90h? followed by a 24-bit address (a23-a0) of 000000h. after which, the manufacturer id and the device id are shifted out on the falling edge of clk with mo st significant bit (msb) first as shown in figure 7.31 . the device id values for the s25fl004k/s25fl008k/s25fl016k is listed in table 7.2, device identification on page 24 . if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids c an be read continuously, alternating from one to the other. the instruction is co mpleted by driving cs# high. figure 7.31 read manufacturer / device id diagram c s # clk s i s o high imped a nce mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 in s tr u ction (90h) addre ss (000000h) 2 3 22 21 3 2 1 0 c s # clk s i s o m a n u f a ct u rer id device id ( ) 7 6 5 4 3 2 1 0 mode 3 mode 0 = m s b 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46
52 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.28 read manufacturer / device id dual i/o (92h) the read manufacturer / device id dual i/o instructi on is an alternative to the read manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 2x speed. the read manufacturer / device id dual i/o instruction is similar to the fast read dual i/o instruction. the instruction is initiated by driving t he cs# pin low and shifting the instruct ion code ?92h? followed by a 24-bit address (a23-a0) of 000000h, but with the capability to input the address bits two bits per clock. after which, the manufacturer id and the device id are shifted out 2 bits per clock on the fa lling edge of clk with most significant bits (msb) first as shown in figure 7.32 . the device id values for the s25fl004k/s25fl008k/ s25fl016k is listed in table 7.2, device identification on page 24 . if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids can be read continuous ly, alternating from one to the other. the instru ction is completed by driving cs# high. figure 7.32 read manufacturer / device id dual i/o diagram note: 1. the ?continuous read mode? bits m(7-0) must be set to fxh to be compatible with fast read dual i/o instruction. c s # clk io1 io0 c s # clk io1 io0
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 53 data sheet 7.29 read manufacturer / device id quad i/o (94h) the read manufacturer / device id quad i/o instruction is an alternative to the r ead manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 4x speed. the read manufacturer / device id quad i/o instruction is similar to the fast read quad i/o instruction. the instruction is initiated by driving the cs# pin low and shifting the instru ction code ?94h? fo llowed by a four clock dummy cycles and then a 24-bit address (a23-a0) of 000000h, but with the c apability to input the address bits four bits per clock. after which, the manufa cturer id and the device id are shifted out four bits per clock on the falling edge of clk with most significant bit (msb) first as shown in figure 7.33 . the device id values for the s25fl004k/s25fl008k/s25fl016k is listed in table 7.2, device identification on page 24 . if the 24-bit address is initially set to 000001h the device id will be read first and then followed by the manufacturer id. the manufacturer and device ids c an be read continuously, alternating from one to the other. the instruction is co mpleted by driving cs# high. figure 7.33 read manufacturer / device id quad i/o diagram note: 1. the ?continuous read mode? bits m(7-0) must be set to fxh to be compatible with fast read quad i/o instruction. c s # clk io1 io0 io 3 io2 c s # clk io1 io0 io 3 io2
54 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.30 read unique id number (4bh) the read unique id number instruction accesses a factory-set read-only 64-bit number that is unique to each s25fl004k/s25fl008k/s25fl016k device. the id number can be used in conjunction with user software methods to help prevent copyi ng or cloning of a system. the read un ique id instruction is initiated by driving the cs# pin low and shifting the instruction code ?4bh? followed by a four bytes of dummy clocks. after which, the 64-bit id is shifted out on the falling edge of clk as shown in figure 7.34 . figure 7.34 read unique id number instruction sequence * * c s # clk s i s o high imped a nce in s tr u ction (4b) d u mmy 1 d u mmy 2 mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 16 17 1 8 19 20 21 22 2 3 c s # clk s i s o = m s b 24 25 26 27 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 101 102 10 3 d u mmy 3 d u mmy 4 64- b it uni qu e s eri a l n u m b er mode 3 mode 0 6 3 62 61 60 59 2 1 0
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 55 data sheet 7.31 read jedec id (9fh) for compatibility reasons, the s25fl004k/s25fl008k /s25fl016k provides several instructions to electronically determine the identity of the devic e. the read jedec id instruct ion is compatible with the jedec standard for spi compatible serial flash memories that was adopted in 2003. the instruction is initiated by driving the cs# pin low and shifting the instruction code ?9fh?. the jedec assigned manufacturer id byte and two device id bytes, memo ry type (id15-id8) and capacity (id7-id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 7.35 . for memory type and capacity values refer to ma nufacturer and device identification table. figure 7.35 read jedec id instruction sequence 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 c s # clk s i s o mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 11 12 1 3 14 15 in s tr u ction (9fh) high imped a nce m a n u f a ct u rer id (efh) c s # clk s i s o mode 3 mode 0 15 16 17 1 8 19 20 21 22 2 3 24 25 26 27 2 8 29 3 0 3 1 memory type id15-id 8 c a p a city id7-id0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 = m s b
56 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.32 read sfdp register (5ah) the s25fl004k/s25fl008k/s25fl016k features a 256-byte serial flash discoverable parameter (sfdp) register that contains in formation about devices operational capabili ty such as available commands, timing and other features. the sfdp parameters are stored in one or more parameter identificat ion (pid) tables. currently only one pid table is specified but more may be added in the future. the read sfdp register instruction is compatible with the sfdp standard init ially established in 2010 for pc and other applications. the read sfdp instruction is initiated by driving the cs# pin low and shifting the instruction code ?5ah? followed by a 24-bit address (a23-a0)( 1) into the si pin. eight ?dummy? clocks are also required before the sfdp register contents are shifted out on the falling edge of the 40th clk wi th most significant bit (msb) first as shown in figure 7.36 . for sfdp register values and descriptions, refer to table 7.6 . note: a23-a8 = 0; a7-a0 are used to define the star ting byte address for the 256-byte sfdp register. figure 7.36 read sfdp register instruction sequence diagram table 7.6 serial flash discoverable paramete r definition table (sheet 1 of 2) byte address data description comment 00h 53h sfdp signature sfdp signature = 50444653h 01h 46h sfdp signature 02h 44h sfdp signature 03h 50h sfdp signature 04h 01h sfdp minor revisions sfdp revision 1.1 05h 01h sfdp major revisions 06h 00h number of parameter headers (nph) 1 parameter header 07h ffh reserved 08h efh pid (3) (0): manufacturer jedec id efh 09h 00h pid(0): serial flash basics minor revisions serial flash basics revision 1.0 0ah 01h pid(0): serial flash basics major revisions c s # clk s i s o mode 3 mode 0 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 in s tr u ction (5ah) 24- b it addre ss 2 3 22 21 3 2 1 0 c s # clk s i s o 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 d u mmy byte d a t a o u t 1 d a t a o u t 2 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 = m s b
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 57 data sheet notes: 1. data stored in byte address 18h to 7fh and 90h to ffh are reserved, the value is ffh. 2. 1 dword = 4 bytes. 3. pid(x) = parameter identification table (x). 0bh 04h pid(0): serial flash basics length 4 dwords (2) 0ch 80h pid(0): address of parameter id(0) table (a7-a0) pid(0) table address = 000080h 0dh 00h pid(0): address of parameter id(0) table (a15-a8) 0eh 00h pid(0): address of parameter id(0) table (a23-a16) 0fh ffh reserved 10h efh pid(1): manufacturer jedec id efh 11h 00h pid(1): serial flash properties minor revisions serial flash properties revision 1.0 12h 01h pid(1): serial flash properties major revisions 13h 00h pid(1): serial flash properties length 00h = unimplemented 14h 90h pid(1): address of parameter id(1) table (a7-a0) pid(1) table address = 000090h 15h 00h pid(1): address of parameter id(1) table (a15-a8) 16h 00h pid(1): address of parameter id(1) table (a23-a16) 17h ffh reserved ... (1) ffh reserved 80h e5h bit[7:5] = 111 reserved bit[4:3] = 00 non-volatile status register bit[2] = 1 page programmable bit[1:0] = 01 supports 4 kb erase 81h 20h 4 kbyte erase opcode 82h f1h bit[7] = 1 reserved bit[6] = 1 supports single input quad output bit[5] = 1 supports quad input quad output bit[4] = 1 supports dual input dual output bit[3] = 0 dual transfer rate not supported bit[2:1] = 00 3-byte/24-bit addressing bit[0] = 1 supports single input dual output 83h ffh reserved 84h ffh flash size in bits 4 megabits = 003fffffh (s25fl004k) 8 megabits = 007fffffh (s25fl008k) 16 megabits = 00ffffffh (s25fl016k) 85h ffh flash size in bits 86h 3fh (s25fl004k) 7fh (s25fl008k) ffh (s25fl016k) flash size in bits 87h 00h flash size in bits 88h 44h bit[7:5] = 010 8 mode bits are needed bit[4:0] = 00100 16 dummy bits are needed fast read quad i/o setting 89h ebh quad input quad output fast read opcode 8ah 08h bit[7:5] = 000 no mode bits are needed bit[4:0] = 01000 8 dummy bits are needed fast read quad output setting 8bh 6bh single input quad output fast read opcode 8ch 08h bit[7:5] = 000 no mode bits are needed bit[4:0] = 01000 8 dummy bits are needed fast read dual output setting 8dh 3bh single input dual output fast read opcode 8eh 80h bit[7:5] = 100 8 mode bits are needed bit[4:0] = 00000 no dummy bits are needed fast read dual i/o setting 8fh bbh dual input dual output fast read opcode ... (1) ffh reserved ffh ffh reserved table 7.6 serial flash discoverable paramete r definition table (sheet 2 of 2) byte address data description comment
58 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.33 erase security registers (44h) the s25fl004k/s25fl008k/s25fl016k offers three 256-b yte security registers which can be erased and programmed individually. thes e registers may be used by the system manufacturers to store security and other important informat ion separately from the main memory array. the erase security register instructi on is similar to the sector erase instruction. a write enable instruction must be executed before the device w ill accept the erase security register instruction (status register bit wel must equal 1). the instruction is initiated by dr iving the cs# pin low and shifting the instruction code ?44h? followed by a 24-bit address (a23-a0) to erase one of the three security registers. the erase security register in struction sequence is shown in figure 7.37 . the cs# pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the instru ction will not be executed. after cs# is driven high, the self-tim ed erase security register operati on will commence for a time duration of t se (see ac electrical characteristics on page 64 ). while the erase security register cycle is in progress, the read status regist er instruction may still be a ccessed for checking the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions agai n. after the erase security re gister cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the security r egister lock bits (lb3:1) in the status register-2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, and an erase security register instruction to that register will be ignored (see security register lock bits (lb3, lb2, lb1) on page 17 ). figure 7.37 erase security regist ers instruction sequence address a23-16 a15-12 a11-8 a7-0 security register #1 00h 0 0 0 1 b 0 0 0 0 b don?t care security register #2 00h 0 0 1 0 b 0 0 0 0 b don?t care security register #3 00h 0 0 1 1 b 0 0 0 0 b don?t care = m s b c s # clk s i s o 0 1 2 3 4 5 6 7 8 9 29 3 0 3 1 in s tr u ction (44h) 24- b it addre ss mode 3 mode 0 mode 3 mode 0 2 3 22 2 1 0 high imped a nce
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 59 data sheet 7.34 program security registers (42h) the program security register instruct ion is similar to the page program in struction. it allows from one byte to 256 bytes of security register dat a to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will ac cept the program security register instruction (status register bit wel= 1). the instru ction is initiated by driving the cs# pin low then shifting the instruction code ?42h? followed by a 24-bit a ddress (a23-a0) and at least one data by te, into the si pin. the cs# pin must be held low for the entire l ength of the instruction while data is being sent to the device. the program security register instruction sequence is shown in figure 7.38 . the security register lock bits (lb3:1) in the status register-2 can be used to otp protec t the security regi sters. once a lock bit is set to 1, the corresponding security register will be permanently lo cked, and a program security register instruction to that register w ill be ignored (see security register lock bits (lb3, lb2, lb1) on page 17 and page program (02h) on page 41 for detail descriptions). figure 7.38 program security regist ers instruction sequence address a23-16 a15-12 a11-8 a7-0 security register #1 00h 0 0 0 1 b 0 0 0 0 b byte address security register #2 00h 0 0 1 0 b 0 0 0 0 b byte address security register #3 00h 0 0 1 1 b 0 0 0 0 b byte address c s # clk s i 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 3 2 33 3 4 3 5 3 6 3 7 38 3 9 in s tr u ction (42h) 24- b it addre ss mode 3 mode 0 d a t a byte 1 2 3 22 21 3 2 1 0 7 6 5 4 3 2 1 0 = m s b c s # clk s i 40 41 42 4 3 44 45 46 47 4 8 49 50 51 52 5 3 54 55 mode 3 mode 0 d a t a byte 2 d a t a byte 3 d a t a byte 256 2072 207 3 2074 2075 2076 207 8 2077 2079 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
60 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 7.35 read security registers (48h) the read security register instructi on is similar to the fast read instruction and allows one or more data bytes to be sequentially read fr om one of the three security registers. t he instruction is initiated by driving the cs# pin low and then shifting t he instruction code ?48h? followed by a 24-bit address (a23-a0) and eight ?dummy? clocks into the si pin. the code and address bi ts are latched on the rising edge of the clk pin. after the address is received, the data byte of the addresse d memory location will be sh ifted out on the so pin at the falling edge of clk with most signi ficant bit (msb) first. the byte address is automatically incremented to the next byte address after each byte of data is shifted ou t. once the byte address r eaches the last byte of the register (byte ffh), it will reset to 00h, the first byte of the register, a nd continue to increment. the instruction is completed by driving cs# high. the read secu rity register instruction sequence is shown in figure 7.39 . if a read security register instruct ion is issued while an erase, program or write cycle is in process (busy=1), the instruction is ignored and will not have any effects on t he current cycle. the read security register instruction al lows clock rates from dc to a maximum of f r (see section 8.6, ac electrical characteristics on page 64 ). figure 7.39 read security registers instruction sequence address a23-16 a15-12 a11-8 a7-0 security register #1 00h 0 0 0 1 b 0 0 0 0 b byte address security register #2 00h 0 0 1 0 b 0 0 0 0 b byte address security register #3 00h 0 0 1 1 b 0 0 0 0 b byte address c s # clk s i s o 0 1 2 3 4 5 6 7 8 9 10 2 8 29 3 0 3 1 mode 3 mode 0 in s tr u ction (4 8 h) 24- b it addre ss 2 3 22 21 3 2 1 0 c s # clk s i s o d u mmy byte d a t a o u t 1 d a t a o u t 2 3 2 33 3 4 3 5 3 6 3 7 38 3 9 40 41 42 4 3 44 45 46 47 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 = m s b
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 61 data sheet 8. electrical characteristics 8.1 absolute maximum ratings notes: 1. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum rati ngs may cause permanen t damage. 2. compliant with jedec standard j-std-20c for small body sn-p b or pb-free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 3. jedec std jesd22-a114a (c1=100 pf, r1=1500 ohms, r2=500 ohms). 8.2 operating ranges note: 1. v cc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage. 8.3 power-up timing and write inhibit threshold note: 1. these parameters are characterized only. parameters (1) symbol conditions range unit supply voltage v cc ?0.6 to +4.0 v voltage applied to any pin v io relative to ground ?0.6 to v cc +0.4 v transient voltage on any pin v iot <20 ns transient relative to ground ?2.0v to v cc +2.0v v storage temperature t stg ?65 to +150 c lead temperature t lead (note 2) c electrostatic discharge voltage v esd human body model (3) ?2000 to +2000 v parameter symbol conditions spec unit s25fl004k s25fl008k s25fl016k min max supply voltage (1) v cc f r = 104 mhz f r = 50 mhz f r = 104 mhz f r = 50 mhz f r = 104 mhz 3.0 3.6 v f r = 80 mhz f r = 50 mhz f r = 80 mhz f r = 50 mhz f r = 70 mhz f r = 50 mhz 2.7 ambient temperature, operating t a industrial ?40 +85 c parameter symbol spec unit min max v cc (min) to cs# low t vsl (1) 10 s time delay before write instruction t puw (1) 1 10 ms write inhibit threshold voltage v wi (1) 1.0 2.0 v
62 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet figure 8.1 power-up timing and voltage levels vcc vcc (m a x) vcc (min) vwi time re s et s t a te re a d in s tr u ction s a llowed device i s f u lly a cce ss i b le progr a m, er as e, a nd write in s tr u ction s a re ignored c s # m us t tr a ck vcc t puw t v s l
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 63 data sheet 8.4 dc electrical characteristics notes: 1. tested on sample basis and specified through design and characterization data. ta = 25c, v cc = 3v. 2. checker board pattern. 8.5 ac measurement conditions note: 1. output high-z is defined as the point where data out is no longer driven. parameter symbol conditions spec unit min typ max input capacitance c in (1) v in = 0v (1) 6 pf output capacitance c out (1) v out = 0v (1) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current (s25fl004k/ s25fl008k) i cc1 cs# = v cc , v in = gnd or v cc 25 50 a standby current (s25fl016k) 10 25 power-down current i cc2 cs# = v cc , v in = gnd or v cc 1 5 a deep power-down current (s25fl016k) i cc2 cs# = v cc , v in = gnd or v cc 1 5 a current: read data / dual /quad 1 mhz (2) i cc3 c = 0.1 v cc / 0.9 v cc so = open 4/5/6 6/7.5/9 ma current: read data / dual /quad 33 mhz (2) i cc3 c = 0.1 v cc / 0.9 v cc so = open 6/7/8 9/10.5/12 ma current: read data / dual output read/ quad output read 50 mhz (2) ( s25fl004k) i cc3 c = 0.1 v cc / 0.9 v cc so = open 7/8/9 10/12/13.5 ma current: read data / dual /quad 50 mhz (2) (s25fl008k/s25fl016k) current: read data / dual output read/ quad output read 80 mhz (2) i cc3 c = 0.1 v cc / 0.9 v cc so = open 10/11/12 15/16.5/18 ma current: write status register (s25fl004k/s25fl008k) i cc4 cs# = v cc 812 ma current: write status register (s25fl016k) 10 15 current page program i cc5 cs# = v cc 20 25 ma current sector/block erase i cc6 cs# = v cc 20 25 ma current chip erase i cc7 cs# = v cc 20 25 ma input low voltage v il v cc x 0.3 v input high voltage v ih v cc x 0.7 v output low voltage v ol i ol = 100 a 0.2 v output high voltage v oh i oh = ?100 a v cc ? 0.2 v parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.2 v cc to 0.8 v cc v input timing reference voltages in 0.3 v cc to 0.7 v cc v output timing reference voltages out 0.5 v cc to 0.5 v cc v
64 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet figure 8.2 ac measurement i/o waveform 8.6 ac electrical characteristics inp u t level s 0. 8 vcc 0.2 vcc 0.5 vcc inp u t a nd o u tp u t timing reference level s table 8.1 ac electrical characteristics (sheet 1 of 2) description symbol alt spec unit min typ max clock frequency for all instructions except for read data instruction (03h) 3.0v-3.6v v cc and industrial temperature (s25fl004k ) f r f c d.c. 104 mhz clock frequency for single/dual spi instructions except for read data instruction (03h) 3.0v-3.6v v cc and industrial temperature (s25fl008k ) clock frequency for all instructions except read data (03h) and octal word read(e3h) 2.7v-3.6v / 3.0v-3.6v (s25fl0016k ) 80 / 104 clock frequency for all instructions except for read data instruction (03h) 2.7v-3.6v v cc and industrial temperature (s25fl004k/ s25fl008k) f r f c d.c. 80 mhz clock frequency for octal word read quad i/o (e3h) 3.0v-3.6v (s25fl0016k ) 50 clock frequency for read data instruction (03h) f r d.c. 50 mhz clock high, low time for all instructions except read data (03h) (s25fl004k) t clh1 , t cll1 (1) t ch , t cl 6 ns clock high, low time except read data (03h) (s25fl008k) 4 clock high, low time except read data (03h) (s25fl016k) t clh , t cll (1) 6 clock high, low time for read data (03h) instruction t crlh , t crll (1) 8 ns clock rise time peak to peak t clch (2) 0.1 v/ns clock fall time peak to peak t chcl (2) 0.1 v/ns cs# active setup time relative to clk t slch t css 5 ns cs# not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 5 ns cs# active hold time relative to clk t chsh 5 ns cs# not active setup time relative to clk t shch 5 ns cs# deselect time (for array read -> array read) t shsl1 t csh 10 ns cs# deselect time (for erase or program -> read status registers) volatile status register write time t shsl2 t csh 50 50 ns output disable time t shqz (2) t dis 7 ns clock low to output valid (s25fl004k) t clqv1 t v1 7 ns clock low to output valid 2.7v-3.6v / 3.0v-3.6v (s25fl008k/s25fl016k) 7 / 6
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 65 data sheet notes: 1. clock high + clock low must be less than or equal to 1/f c . 2. value guaranteed by design and/or characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when sector protect bit is set to 1. 4. for multiple bytes after first byte within a page, t bpn = t bp1 + t bp2 * n (typical) and t bpn = t bp1 + t bp2 * n (max), where n = number of bytes programmed. 5. max value t se with <50k cycles is 200 ms and >50k and <100k cycles is 400 ms. clock low to output valid (for read id instructions) (s25fl004k) t clqv2 t v2 7.5 ns clock low to output valid (for read id instructions) 2.7v-3.6v / 3.0v-3.6v ( s25fl008k/s25fl016k) 8.5 / 7.5 output hold time t clqx t ho 0 ns hold# active setup time relative to clk t hlch 5 ns hold# active hold time relative to clk t chhh 5 ns hold# not active setup time relative to clk t hhch 5 ns hold# not active hold time relative to clk t chhl 5 ns hold# to output low-z t hhqx (2) t lz 7 ns hold# to output high-z t hlqz (2) t hz 12 ns write protect setup time before cs# low t whsl (3) 20 ns write protect hold time after cs# high t shwl (3) 100 ns cs# high to power-down mode t dp (2) 3 s cs# high to standby mode without electronic signature read t res1 (2) 3 s cs# high to standby mode with electronic signature read t res2 (2) 1.8 s cs# high to next instruction after suspend t sus (2) 20 s write status register time t w 10 15 ms byte program time (first byte) (4) (s25fl004k) t bp1 20 50 s byte program time (first byte) (4) (s25fl008k/s25fl016k) 30 additional byte program time (after first byte) (4) t bp2 2.5 12 s page program time t pp 0.7 3 ms sector erase time (4 kb) t se 30 200/400 (5) ms block erase time (32 kb) t be1 120 800 ms block erase time (64 kb) t be2 150 1,000 ms chip erase time (s25fl004k) t ce 14 s chip erase time (s25fl008k) 26 chip erase time (s25fl016k) 310 table 8.1 ac electrical characteristics (sheet 2 of 2) description symbol alt spec unit min typ max
66 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 8.7 serial output timing figure 8.3 serial output timing 8.8 serial input timing figure 8.4 serial input timing 8.9 hold timing figure 8.5 hold timing * s io i s a n o u tp u t only for the f as t re a d d ua l o u tp u t in s tr u ction s ( 3 bh) c s # clk s o/ s io* l s b o u t t clqx t clqv t clqx t clqv t clh t cll t qlqh t qhql t s hqz c s # clk s io s o (high imped a nce) m s b in l s b in t ch s l t s lch t dvch t chdx t ch s h t s hch t clch t chcl t s h s l c s # clk s io s o hold# t hlch t hhch t hhqx t chhh t hlqz t chhl
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 67 data sheet 9. physical dimensions 9.1 soa008 narrow ? 8-pin plastic small outline package (150-mils body width) package s oa 00 8 (inche s ) s oa 00 8 (mm) jedec m s -012(d)aa m s -012(d)aa s ymbol min max min max a 0.05 3 1 0.06 88 1. 3 5 1.75 a1 0.00 3 9 0.009 8 0.10 0.25 a2 0.052 0.061 1. 3 2 1.55 b 0.012 0.020 0. 3 1 0.51 b 1 0.011 0.019 0.27 0.4 8 c 0.0067 0.009 8 0.17 0.25 c1 0.0067 0.009 0.17 0.2 3 d 0.19 3 b s c 4.90 b s c e 0.2 3 6 b s c 6.00 b s c e1 0.15 3 5 b s c 3 .90 b s c e .050 b s c 1.27 b s c l 0.0161 0.0 3 5 0.41 0. 8 9 l1 .041 ref 1.04 ref l2 .010 b s c 0.25 b s c n 8 8 h 0.10 0.196 0.25 0.50 0? 8 ?0? 8 ? 1 5? 15? 5? 15? 2 0? 0? 3 52 8 \ 16-0 38 .0 3 \ 11.02.05 note s : 1. all dimen s ion s are in both inche s and millmeter s . 2. dimen s ioning and tolerancing per a s me y14.5m - 1994. 3 . dimen s ion d doe s not include mold fla s h, protru s ion s or gate burr s . mold fla s h, protru s ion s or gate burr s s hall not exceed 0.15 mm per end. dimen s ion e1 doe s not include interlead fla s h or protru s ion interlead fla s h or protru s ion s hall not exceed 0.25 mm per s ide. d and e1 dimen s ion s are determined at datum h. 4. the package top may be s maller than the package bottom. dimen s ion s d and e1 are determined at the outmo s t extreme s of the pla s tic body exclu s ive of mold fla s h, tie bar burr s , gate burr s and interlead fla s h. but including any mi s match between the top and bottom of the pla s tic body. 5. datum s a and b to be determined at datum h. 6. "n" i s the maximum number of terminal po s ition s for the s pecified package length. 7. the dimen s ion s apply to the flat s ection of the lead between 0.10 to 0.25 mm from the lead tip. 8 . dimen s ion " b " doe s not include dambar protru s ion. allowable dambar protru s ion s hall be 0.10 mm total in exce ss of the " b " dimen s ion at maximum material condition. the dambar cannot be located on the lower radiu s of the lead foot. 9. thi s chamfer feature i s optional. if it i s not pre s ent, then a pin 1 identifier mu s t be located within the index area indicated. 10. lead coplanarity s hall be within 0.10 mm a s mea s ured from the s eating plane. . 9 c a a1 a2 b e 5 b d e e/2 5 e1/2 4 3 e1 3 s eating plane 4 d a 0.10 c 0.10 c a - b 0.20 c a - b cd 0.25 m (0.25d x 0.75e) index area 0. 33 c h 9 h h s ee detail b b 1 c1 7 ( b ) c with plating ba s e metal s ection a-a 2 0 0.07 r min. 1 0 l1 c 0 l2 a a l gauge plane s eating plane h detail b
68 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet 9.2 soc008 wide ? 8-pin plas tic small outline package (208-mils body width) 3 602 \ 16-0 38 .0 3 \ 9.1.6 note s : 1. all dimen s ion s are in both inche s and millmeter s . 2. dimen s ioning and tolerancing per a s me y14.5m - 1994. 3 .dimen s ion d doe s not include mold fla s h, protru s ion s or gate burr s . mold fla s h, protru s ion s or gate burr s s hall not exceed 0.15 mm per end. dimen s ion e1 doe s not include interlead fla s h or protru s ion interlead fla s h or protru s ion s hall not exceed 0.25 mm per s ide. d and e1 dimen s ion s are determined at datum h. 4. the package top may be s maller than the package bottom. dimen s ion s d and e1 are determined at the outmo s t extreme s of the pla s tic body exclu s ive of mold fla s h, tie bar burr s , gate burr s and interlead fla s h. but including any mi s match between the top and bottom of the pla s tic body. 5. datum s a and b to be determined at datum h. 6. "n" i s the maximum number of terminal po s ition s for the s pecified package length. 7. the dimen s ion s apply to the flat s ection of the lead between 0.10 to 0.25 mm from the lead tip. 8 . dimen s ion " b " doe s not include dambar protru s ion. allowable dambar protru s ion s hall be 0.10 mm total in exce ss of the " b " dimen s ion at maximum material condition. the dambar cannot be located on the lower radiu s of the lead foot. 9. thi s chamfer feature i s optional. if it i s not pre s ent, then a pin 1 identifier mu s t be located within the index area indicated. 10. lead coplanarity s hall be within 0.10 mm a s mea s ured from the s eating plane. package s oc 00 8 (inche s ) s oc 00 8 (mm) jedec s ymbol min max min max a 0.069 0.0 8 5 1.75 3 2.159 a1 0.002 0.009 8 0.051 0.249 a2 0.067 0.075 1.70 1.91 b 0.014 0.019 0. 3 56 0.4 83 b 10.01 3 0.01 8 0. 33 00.457 c 0.0075 0.0095 0.191 0.241 c1 0.006 0.00 8 0.152 0.20 3 d 0.20 8 b s c 5.2 83 b s c e 0. 3 15 b s c 8 .001 b s c e1 0.20 8 b s c 5.2 83 b s c e .050 b s c 1.27 b s c l 0.020 0.0 3 00.50 8 0.762 l1 .049 ref 1.25 ref l2 .010 b s c 0.25 b s c n 8 8 0? 8 ?0? 8 ? 1 5? 15? 5? 15? 2 0? 0?
july 14, 2011 s25fl004k-016k_00_02 s25fl004k / s25fl008k / s25fl016k 69 data sheet 10. revision history section description revision 01 (june 10, 2011) initial release. combined s25fl004k_00_02, s25fl008k_00_02, and s25fl016k_00_02. revision 02 (july 14, 2011) global promoted data sheet designation from preliminary to full production
70 s25fl004k / s25fl008k / s25fl016k s25fl004k-016k_00_02 july 14, 2011 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any ot her warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2011 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand?, ecoram? and combinations thereof, are trademarks and registered trademarks of spansion llc in the united states and other countries. ot her names used are for informational purposes only and may be trademarks of their respective owners.

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